gd32f3x0_spi_it.c 2.9 KB

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  1. /*!
  2. \file gd32f3x0_it.c
  3. \brief interrupt service routines
  4. \version 2017-06-06, V1.0.0, firmware for GD32F3x0
  5. \version 2019-06-01, V2.0.0, firmware for GD32F3x0
  6. \version 2020-09-30, V2.1.0, firmware for GD32F3x0
  7. \version 2022-01-06, V2.2.0, firmware for GD32F3x0
  8. \version 2022-04-15, V2.2.1, firmware for GD32F3x0
  9. */
  10. /*
  11. Copyright (c) 2022, GigaDevice Semiconductor Inc.
  12. Redistribution and use in source and binary forms, with or without modification,
  13. are permitted provided that the following conditions are met:
  14. 1. Redistributions of source code must retain the above copyright notice, this
  15. list of conditions and the following disclaimer.
  16. 2. Redistributions in binary form must reproduce the above copyright notice,
  17. this list of conditions and the following disclaimer in the documentation
  18. and/or other materials provided with the distribution.
  19. 3. Neither the name of the copyright holder nor the names of its contributors
  20. may be used to endorse or promote products derived from this software without
  21. specific prior written permission.
  22. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  25. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  26. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  28. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  29. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  31. OF SUCH DAMAGE.
  32. */
  33. #include "gd32f3x0_it.h"
  34. extern uint8_t spi0_send_array[ ];
  35. extern uint8_t spi1_receive_array[ ];
  36. extern volatile uint32_t send_n, receive_n ;
  37. void SPI0_IRQHandler(void)
  38. {
  39. if(RESET != spi_i2s_interrupt_flag_get(SPI0, SPI_I2S_INT_FLAG_TBE)) {
  40. /* send data */
  41. spi_i2s_data_transmit(SPI0, spi0_send_array[send_n++]);
  42. if(ARRAYSIZE == send_n) {
  43. #if SPI_CRC_ENABLE
  44. /* send the CRC value */
  45. spi_crc_next(SPI0);
  46. #endif /* enable CRC function */
  47. spi_i2s_interrupt_disable(SPI0, SPI_I2S_INT_TBE);
  48. }
  49. }
  50. }
  51. /*!
  52. \brief this function handles SPI1 Handler exception
  53. \param[in] none
  54. \param[out] none
  55. \retval none
  56. */
  57. void SPI1_IRQHandler(void)
  58. {
  59. /* receive data */
  60. if(RESET != spi_i2s_interrupt_flag_get(SPI1, SPI_I2S_INT_FLAG_RBNE)) {
  61. spi1_receive_array[receive_n++] = spi_i2s_data_receive(SPI1);
  62. #if SPI_CRC_ENABLE
  63. if((ARRAYSIZE - 1) == receive_n) {
  64. /* receive the CRC value */
  65. spi_crc_next(SPI1);
  66. }
  67. #endif /* enable CRC function */
  68. }
  69. }