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断路器通断监测V2.0
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IO断路器V2.0
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Design Rule Check - DLQ.drc

Design Rule Check - DLQ.drc 1.4 KB
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  1. Protel Design System Design Rule Check
    2. 

  2. PCB File : D:\¶Ï·Æ÷ͨ¶Ï¼à²âV2.0\IO¶Ï·Æ÷V2.0\DLQ.pcbdoc
    3. 

  3. Date     : 2024/8/28
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  4. Time     : 17:36:53
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  5. 

  6. Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
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  7. Rule Violations :0
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  8. 

  9. Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
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  10. Rule Violations :0
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  11. 

  12. Processing Rule : Un-Routed Net Constraint ( (All) )
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  13. Rule Violations :0
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  14. 

  15. Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
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  16. Rule Violations :0
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  17. 

  18. Processing Rule : Width Constraint (Min=0.1mm) (Max=3mm) (Preferred=0.254mm) (All)
    19. 

  19. Rule Violations :0
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  20. 

  21. Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
    22. 

  22. Rule Violations :0
    23. 

  23. 

  24. Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
    25. 

  25. Rule Violations :0
    26. 

  26. 

  27. Processing Rule : Hole To Hole Clearance (Gap=0mm) (All),(All)
    28. 

  28. Rule Violations :0
    29. 

  29. 

  30. Processing Rule : Minimum Solder Mask Sliver (Gap=0mm) (All),(All)
    31. 

  31. Rule Violations :0
    32. 

  32. 

  33. Processing Rule : Silk To Solder Mask (Clearance=0mm) (IsPad),(All)
    34. 

  34. Rule Violations :0
    35. 

  35. 

  36. Processing Rule : Silk to Silk (Clearance=0mm) (All),(All)
    37. 

  37. Rule Violations :0
    38. 

  38. 

  39. Processing Rule : Net Antennae (Tolerance=0mm) (All)
    40. 

  40. Rule Violations :0
    41. 

  41. 

  42. Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
    43. 

  43. Rule Violations :0
    44. 

  44. 

  45. 

  46. Violations Detected : 0
    47. 

  47. Waived Violations : 0
    48. 

  48. Time Elapsed        : 00:00:02
    49.