双火线，整改代码。

truing_control/PDU-Triphasic_IO/HARDWARE/ReadEeprom/ReadEeprom.c

@@ -259,12 +259,12 @@ void  ReadEeprom(void)
 		{
 				AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] = 0;			
 		}
-		for(int i = 0 ; i < 4;i++)
+		for(int i = 0 ; i < Output_ChN_default;i++)
 		{
-			AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] = Eeprom_Rbuf[ERom_SINGLE_OUT_CH_Addr+i];
-			if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] > 3)
+			AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] = Eeprom_Rbuf[ERom_CH_CTRL_Addr+i];
+			if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] > 2)
 			{
-				AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] = 0;
+				AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] = 0;
 			}
 		}
 }

truing_control/PDU-Triphasic_IO/Modbus/BARE/port/port.c

@@ -179,7 +179,7 @@ eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegi
 							usNRegs--;
 						}
 						{
-							if((usAddress >= AC3PPDU_ViLit_max_Addr)&&(usAddress <= AC3PPDU_BREAK_UPGRADE))
+							if((usAddress >= AC3PPDU_ViLit_max_Addr)&&(usAddress <= AC3PPDU_CH9_CTRL))
 							{
 								
 								{

truing_control/PDU-Triphasic_IO/USER/main.c

@@ -528,55 +528,29 @@ static void RL_Over_Func()
 
 		for(int i = 0; i < Output_ChN_default;i++)
 		{
-			AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xffffff3e;
-			orderFlag[i]=true;
+			if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
+			{
+				AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xffffff3e;
+				orderFlag[i]=true;
+			}
 		}
 		RL_All_Func = 0;
 		return;
 	}
-#if SUPPORT_DOUBLE_FIRE
-	
-	for(int i = 0; i < PH_STEP;i++)
+
+	for(int i = 0; i < Output_ChN_default;i++)
 	{
-		if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+		if(RL_Func_statu[i+1])
 		{
-			if(RL_Func_statu[i+1] || RL_Func_statu[i+1+PH_STEP])
+			if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
 			{
 				RL_Func_statu[i+1] = 0;
-				RL_Func_statu[i+1+PH_STEP] = 0;
 				AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xffffff3e;
-				AC3PPDU_RL_time[i + CH1_out+PH_STEP].LT_state = AC3PPDU_RL_time[i + CH1_out+PH_STEP].LT_state &0xffffff3e;
 				orderFlag[i]=true;
-				orderFlag[i+PH_STEP]=true;
 			}
-		}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
-		{
-			if(RL_Func_statu[i+1]){
-				RL_Func_statu[i+1] = 0;
-				AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xffffff3e;
-				orderFlag[i]=true;
-			}
-		}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-		{
-			if(RL_Func_statu[i+1+PH_STEP])
-			{
-				RL_Func_statu[i+1+PH_STEP] = 0;
-				AC3PPDU_RL_time[i + CH1_out+PH_STEP].LT_state = AC3PPDU_RL_time[i + CH1_out+PH_STEP].LT_state &0xffffff3e;
-				orderFlag[i+PH_STEP]=true;		
-			}				
-		}
-	}
-#else
-	for(int i = 0; i < Output_ChN_default;i++)
-	{
-		if(RL_Func_statu[i+1])
-		{
-			AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xffffff3e;
-			orderFlag[i]=true;
 			RL_Func_statu[i+1] = 0;
 		}
 	}
-#endif
 }
 
 static void key_io_control()
@@ -593,9 +567,7 @@ void switch_recode()
 #if SUPPORT_DETECTION
 #if SUPPORT_DETECT_REMENBER
 	#if SUPPORT_DOUBLE_FIRE
-	
 	uint8_t sync_buff[PH_STEP] = {0};
-	
 	if(detection_value != 0x3)
 	{
 		if((detection_value & 0x1) == 0)
@@ -604,7 +576,7 @@ void switch_recode()
 			{
 				for(int i= 0; i < PH_STEP;i++)
 				{
-					if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+					if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 					{
 						handle_status[i] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
 						AC3PPDU_RL_time[i + CH1_out].LT_state &= 0xffffff7e;
@@ -613,17 +585,6 @@ void switch_recode()
 						AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state &= 0xffffff7e;
 						orderFlag[i+PH_STEP]=true;		
 						sync_buff[i] = 1;
-					}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
-					{
-						handle_status[i] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
-						AC3PPDU_RL_time[i + CH1_out].LT_state &= 0xffffff7e;
-						orderFlag[i]=true;	
-						AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state &= 0xffffff7e;
-						orderFlag[i+PH_STEP]=true;						
-					}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-					{
-						AC3PPDU_RL_time[i + CH1_out].LT_state &= 0xffffff7e;
-						orderFlag[i]=true;
 					}
 				}
 				handle_detection[0] = 0;
@@ -636,7 +597,7 @@ void switch_recode()
 			{
 				for(int i= 0; i < PH_STEP;i++)
 				{
-					if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+					if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 					{
 						if(sync_buff[i])
 						{
@@ -649,17 +610,6 @@ void switch_recode()
 							AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state &= 0xffffff7e;
 							orderFlag[i+PH_STEP]=true;		
 						}
-					}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
-					{
-						AC3PPDU_RL_time[i + CH1_out].LT_state &= 0xffffff7e;
-						orderFlag[i]=true;					
-					}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-					{
-						handle_status[i + PH_STEP] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i +PH_STEP] & 0x1);
-						AC3PPDU_RL_time[i + CH1_out+PH_STEP].LT_state &= 0xffffff7e;
-						orderFlag[i+PH_STEP]=true;
-						AC3PPDU_RL_time[i + CH1_out].LT_state &= 0xffffff7e;
-						orderFlag[i]=true;						
 					}
 				}
 				handle_detection[1] = 0;
@@ -672,7 +622,7 @@ void switch_recode()
 			handle_detection[0] = 1;
 			for(int i = 0; i < PH_STEP;i++)
 			{
-				if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+				if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0  && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 				{
 					AC3PPDU_RL_time[i + CH1_out].LT_state |= 0x40;
 					AC3PPDU_RL_time[i + CH1_out].LT_state |= handle_status[i];
@@ -681,14 +631,6 @@ void switch_recode()
 					AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state |= handle_status[i+PH_STEP];
 					orderFlag[i+PH_STEP]=true;
 					sync_buff[i] = 1;					
-				}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
-				{
-					AC3PPDU_RL_time[i + CH1_out].LT_state |= 0x40;
-					AC3PPDU_RL_time[i + CH1_out].LT_state |= handle_status[i];
-					orderFlag[i]=true;					
-				}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-				{
-					
 				}
 			}
 		}
@@ -697,7 +639,7 @@ void switch_recode()
 			handle_detection[1] = 1;
 			for(int i = 0; i < PH_STEP;i++)
 			{
-				if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+				if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 				{
 					if(sync_buff[i])
 					{
@@ -711,14 +653,6 @@ void switch_recode()
 						AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state |= handle_status[i+PH_STEP];
 						orderFlag[i+PH_STEP]=true;						
 					}
-				}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
-				{
-					
-				}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-				{
-					AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state |= 0x40;
-					AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state |= handle_status[i+PH_STEP];
-					orderFlag[i + PH_STEP]=true;								
 				}
 			}
 		}
@@ -925,22 +859,15 @@ int main(void)
 			{
 				for(int i = 0; i < PH_STEP; i++)
 				{
-					if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+					if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 					{
 						handle_status[i] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
 						AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
 						handle_status[i + PH_STEP] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i +PH_STEP] & 0x1);
 						AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + PH_STEP] &= 0xfffffffe;
-					}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
-					{
-						handle_status[i] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
-						AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
-					}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-					{
-						AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
 					}
-				}
 				handle_detection[0] = 0;
+				}
 			}else
 			{
 				;;;
@@ -952,41 +879,18 @@ int main(void)
 			{
 				for(int i = 0; i < PH_STEP; i++)
 				{
-					if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+					if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 					{
 						handle_status[i] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
 						AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
 						handle_status[i + PH_STEP] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i +PH_STEP] & 0x1);
 						AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + PH_STEP] &= 0xfffffffe;						
-					}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
-					{
-						AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + PH_STEP] &= 0xfffffffe;						
-					}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-					{
-						handle_status[i+PH_STEP] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i+PH_STEP] & 0x1);
-						AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + PH_STEP] &= 0xfffffffe;						
 					}
 				}
 			}
 			handle_detection[1] = 0;
 		}
-	}else
-	{
-		for(int i = 0; i < PH_STEP; i++)
-		{
-			if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
-			{
-				;;
-			}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
-			{
-				AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + PH_STEP] &= 0xfffffffe;		
-			}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-			{
-				AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;		
-			}
-		}
 	}
-
 #else
 	if(detection_value == 0)
 	{
@@ -1037,8 +941,17 @@ int main(void)
 	for(int i = 0;i < Output_ChN_default;i++)
 	{
 		RL_last_state[i] = 0;
-		AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i];
-		AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
+		if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
+		{
+			AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i];
+		}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 1)
+		{
+			AC3PPDU_RL_time[i + CH1_out].LT_state = 1;
+		}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 2)
+		{
+			AC3PPDU_RL_time[i + CH1_out].LT_state = 0;
+		}
+			AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
 		AC3PPDU_RL_time[i + CH1_out].RL_ontime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Ton1_Addr + i];
 		AC3PPDU_RL_time[i + CH1_out].RL_offtime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Toff1_Addr + i];
 		LimiT_enable_check((i + CH1_out),AC3PPDU_RL_time[i + CH1_out].LT_state);
@@ -1256,7 +1169,7 @@ static void MODbus_CMD_New(void)
 						{
 							for(i = 0;i < PH_STEP;i++)
 							{
-								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 								{
 									temp_addr = i << 1; 
 									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
@@ -1268,19 +1181,12 @@ static void MODbus_CMD_New(void)
 									//AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
 									RL_Allon_flag = false;
 									sync_buff[i] = 1;
-								}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
+								}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
 								{
 									temp_addr = i << 1; 
 									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
 									AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
-									orderFlag[i]=true;		
-									temp_addr = (i+PH_STEP) << 1; 
-									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
-									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;									
-								}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-								{
-									;;
-
+									orderFlag[i]=true;								
 								}
 							}							
 						}
@@ -1288,7 +1194,7 @@ static void MODbus_CMD_New(void)
 						{
 							for(i = 0;i < PH_STEP;i++)
 							{
-								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 								{
 									
 									if(sync_buff[i])
@@ -1304,17 +1210,9 @@ static void MODbus_CMD_New(void)
 										Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;	
 										RL_Allon_flag = false;
 									}
-								}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
+								}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
 								{
-
-									
-								}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-								{
-									temp_addr = i << 1; 
-									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
-									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
-									
-									temp_addr = (i+PH_STEP) << 1; 
+									temp_addr = (i+PH_STEP) << 1;
 									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
 									AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
 									orderFlag[i+PH_STEP]=true;										
@@ -1325,7 +1223,7 @@ static void MODbus_CMD_New(void)
 					{
 						for(i = 0;i < PH_STEP;i++)
 						{
-							if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
+							if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 							{
 								temp_addr = i << 1; 
 								Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
@@ -1335,24 +1233,22 @@ static void MODbus_CMD_New(void)
 								Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
 								AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
 								orderFlag[i+PH_STEP]=true;								
-							}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
+							}else 
 							{
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
+								{
 									temp_addr = i << 1; 
 									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
 									AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
 									orderFlag[i]=true;
-									temp_addr = (i+PH_STEP) << 1; 
-									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
-									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;								
-							}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
-							{
-									temp_addr = i << 1; 
-									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
-									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
-									temp_addr = (i+PH_STEP) << 1; 
+								}
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
+								{
+									temp_addr = (i+PH_STEP) << 1;
 									Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
 									AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
 									orderFlag[i+PH_STEP]=true;									
+								}
 							}
 						}		
 					}
@@ -1462,11 +1358,14 @@ static void MODbus_CMD_New(void)
 					RL_Alloff_flag = true;
 					for(i = 0;i < Output_ChN_default;i++)
 					{
-						temp_addr = i << 1;
-						Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
-						Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
-						AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
-						orderFlag[i]=true;
+						if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
+						{
+							temp_addr = i << 1;
+							Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
+							Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
+							AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
+							orderFlag[i]=true;
+						}
 					}
 					AT24CxxWrite(ERom_CH1LT_ST_Addr,(Eeprom_Rbuf + ERom_CH1LT_ST_Addr),(2*Output_ChN_default));
 		#if SUPPORT_ZERO_LINE
@@ -1528,44 +1427,45 @@ static void MODbus_CMD_New(void)
 					}
 #if SUPPORT_DETECTION
 	#if SUPPORT_DOUBLE_FIRE
+
 					if(detection_value != 0x3)
 					{
-						if(detection_value & 0x1)
+						for(i = 0;i < PH_STEP;i++)
 						{
-							if(temp_addr < PH_STEP)
+							if(temp_addr == i || (temp_addr == (i+ PH_STEP)))
 							{
-								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+temp_addr] == 1)
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
 								{
-
+									break;
+								}else
+								{
+									if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
+									{
 										AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
 										orderFlag[temp_addr]=true;
 										LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
 										temp_addr = temp_addr << 1;
 										temp_addr += ERom_CH1LT_ST_Addr;
 										Eeprom_Rbuf[temp_addr] = data;
-										AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
+										AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);										
+									}
+									if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
+									{
+										AC3PPDU_RL_time[temp_addr + CH1_out+PH_STEP].LT_state = data;
+										orderFlag[temp_addr+PH_STEP]=true;
+										LimiT_enable_check((temp_addr + CH1_out+PH_STEP),AC3PPDU_RL_time[temp_addr + CH1_out+PH_STEP].LT_state);
+										temp_addr = temp_addr << 1;
+										temp_addr += ERom_CH1LT_ST_Addr;
+										Eeprom_Rbuf[temp_addr] = data;
+										AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);										
+									}
+									break;
 								}
-							}	
-						}
-						if(detection_value & 0x2)
-						{
-							if(temp_addr >= PH_STEP)
-							{
-								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+temp_addr] == 2)
-								{
-									AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
-									orderFlag[temp_addr]=true;
-									LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
-									temp_addr = temp_addr << 1;
-									temp_addr += ERom_CH1LT_ST_Addr;
-									Eeprom_Rbuf[temp_addr] = data;
-									AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);												
-								}		
 							}
 						}
 					}else
 					{
-						if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+temp_addr] == 0)
+						if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+temp_addr] == 0)
 						{
 							AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
 							orderFlag[temp_addr]=true;
@@ -1573,33 +1473,10 @@ static void MODbus_CMD_New(void)
 							temp_addr = temp_addr << 1;
 							temp_addr += ERom_CH1LT_ST_Addr;
 							Eeprom_Rbuf[temp_addr] = data;
-							AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);								
-						}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+temp_addr] == 1)
-						{
-							if(temp_addr < PH_STEP)
-							{
-								AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
-								orderFlag[temp_addr]=true;
-								LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
-								temp_addr = temp_addr << 1;
-								temp_addr += ERom_CH1LT_ST_Addr;
-								Eeprom_Rbuf[temp_addr] = data;
-								AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);								
-							}
-						}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+temp_addr] == 2)
-						{
-							if(temp_addr >= PH_STEP)
-							{
-								AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
-								orderFlag[temp_addr]=true;
-								LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
-								temp_addr = temp_addr << 1;
-								temp_addr += ERom_CH1LT_ST_Addr;
-								Eeprom_Rbuf[temp_addr] = data;
-								AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);														
-							}
+							AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);									
 						}
 					}
+
 	#else 
 					if(detection_value == 1)
 					{
@@ -1661,37 +1538,51 @@ static void MODbus_CMD_New(void)
 		#endif
 					{
 						temp_addr = base_addr - Mb_Dbuff_OUTCH1_ST_Addr;
-						for(int i = temp_addr; i < Output_ChN_default; i += 4)
+						for(int i = temp_addr; i < Output_ChN_default; i += PH_STEP)
 						{
-							uint32_t value = data;
-							if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + i] <= THRESHOULD_JUDGMENT)
-							{
-								value &= Shield_Vmax_Threshould_Disable;
-							}		
-							if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + i] <= THRESHOULD_JUDGMENT)
-							{
-								value &= (Shield_Vmin_Threshould_Disable);
-							}		
-							if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + i] <= THRESHOULD_JUDGMENT)
-							{
-								value &=(Shield_Imax_Threshould_Disable);
-							}
-							if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + i] <= THRESHOULD_JUDGMENT)
+							if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
 							{
-								value &=(Shield_Wmax_Threshould_Disable);
+								if(i >=PH_STEP)
+								{
+									if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i-PH_STEP] != 0)
+									{
+										continue;
+									}
+								}else
+								{
+									if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] != 0)
+										continue;
+								}
+								uint32_t value = data;
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + i] <= THRESHOULD_JUDGMENT)
+								{
+									value &= Shield_Vmax_Threshould_Disable;
+								}		
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + i] <= THRESHOULD_JUDGMENT)
+								{
+									value &= (Shield_Vmin_Threshould_Disable);
+								}		
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + i] <= THRESHOULD_JUDGMENT)
+								{
+									value &=(Shield_Imax_Threshould_Disable);
+								}
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + i] <= THRESHOULD_JUDGMENT)
+								{
+									value &=(Shield_Wmax_Threshould_Disable);
+								}
+								if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + i] <= THRESHOULD_JUDGMENT)
+								{
+									value &= (Shield_Kwhmax_Threshould_Disable);
+								}	
+								
+								AC3PPDU_RL_time[i + CH1_out].LT_state = value;
+								uint16_t val = i;
+								val <<=1;
+								orderFlag[i]=true;
+								LimiT_enable_check((i + CH1_out),AC3PPDU_RL_time[i + CH1_out].LT_state);
+								Eeprom_Rbuf[val + ERom_CH1LT_ST_Addr] = value;
+								AT24CxxWriteOneByte(val + ERom_CH1LT_ST_Addr,Eeprom_Rbuf[val + ERom_CH1LT_ST_Addr]);
 							}
-							if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + i] <= THRESHOULD_JUDGMENT)
-							{
-								value &= (Shield_Kwhmax_Threshould_Disable);
-							}	
-							
-							AC3PPDU_RL_time[i + CH1_out].LT_state = value;
-							uint16_t val = i;
-							val <<=1;
-							orderFlag[i]=true;
-							LimiT_enable_check((i + CH1_out),AC3PPDU_RL_time[i + CH1_out].LT_state);
-							Eeprom_Rbuf[val + ERom_CH1LT_ST_Addr] = value;
-							AT24CxxWriteOneByte(val + ERom_CH1LT_ST_Addr,Eeprom_Rbuf[val + ERom_CH1LT_ST_Addr]);
 						}
 					}
 #else
@@ -1791,6 +1682,7 @@ static void MODbus_CMD_New(void)
 				AT24CxxWriteOneByte(ERom_RL_ToffN_Addr,Eeprom_Rbuf[ERom_RL_ToffN_Addr]);
 			}
 				break;
+#if 0
 			case Mb_Dbuff_RL_SET_SINGLE_OUT_CH1 ... Mb_Dbuff_RL_SET_SINGLE_OUT_CH4:
 			{
 				temp_addr = base_addr - Mb_Dbuff_RL_SET_SINGLE_OUT_CH1;
@@ -1807,8 +1699,10 @@ static void MODbus_CMD_New(void)
 			}				
 				
 #endif
+	
 			}
 			break;
+#endif
 			case Mb_Dbuff_RL_Over_Ch1_Func ... Mb_Dbuff_RL_Over_Ch9_Func:					//threod over limit operation
 			{
 				temp_addr = base_addr - Mb_Dbuff_RL_Over_Ch1_Func;
@@ -1924,6 +1818,38 @@ static void MODbus_CMD_New(void)
 				break_2_boot_upgreade();
 			}
 			break;
+			case Mb_Dbuff_Ch1_Ctrl_Addr ... Mb_Dbuff_Ch9_Ctrl_Addr:
+			{
+				temp_addr = base_addr - Mb_Dbuff_Ch1_Ctrl_Addr;
+				uint8_t _val = temp_addr;
+				temp_addr = temp_addr << 1; 
+				
+				
+				temp_addr += Mb_Dbuff_Ch1_Ctrl_Addr;
+				Eeprom_Rbuf[temp_addr] = data;
+				AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr + _val] = Eeprom_Rbuf[temp_addr];
+				
+				if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr + _val] == 1)
+				{
+					Eeprom_Rbuf[ERom_CH1LT_ST_Addr+ (_val << 1)] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + (_val << 1)] | 0x41;
+					AC3PPDU_RL_time[_val + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr +(_val << 1)];
+					orderFlag[_val]=true;
+					AT24CxxWriteOneByte(ERom_CH1LT_ST_Addr + _val,Eeprom_Rbuf[ERom_CH1LT_ST_Addr+ (_val << 1)]);		
+				}else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr + _val] == 2)
+				{
+					Eeprom_Rbuf[ERom_CH1LT_ST_Addr+ (_val << 1)] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + (_val << 1)] & (~0x1);
+					AC3PPDU_RL_time[_val + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr +(_val << 1)];
+					orderFlag[_val]=true;
+					AT24CxxWriteOneByte(ERom_CH1LT_ST_Addr + _val,Eeprom_Rbuf[ERom_CH1LT_ST_Addr+ (_val << 1)]);			
+				}else
+				{
+					AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr + _val] = 0;
+					Eeprom_Rbuf[Mb_Dbuff_Ch1_Ctrl_Addr + _val] = 0;
+				}
+	
+				AT24CxxWriteOneByte(ERom_CH_CTRL_Addr+_val,Eeprom_Rbuf[temp_addr]);
+			}
+			break;
 			default:
 				break;
 		}

truing_control/PDU-Triphasic_IO/USER/main.h

@@ -202,10 +202,10 @@
 #define Mb_Dbuff_RL_LackB_Addr				231						// add by liyi
 #define Mb_Dbuff_RL_LackC_Addr				232						// add by liyi
 
-#define Mb_Dbuff_RL_SET_SINGLE_OUT_CH1       233    //add by liyi
-#define Mb_Dbuff_RL_SET_SINGLE_OUT_CH2       234		//add by liyi
-#define Mb_Dbuff_RL_SET_SINGLE_OUT_CH3       235    //add by liyi
-#define Mb_Dbuff_RL_SET_SINGLE_OUT_CH4       236    //add by liyi
+//#define Mb_Dbuff_RL_SET_SINGLE_OUT_CH1       233    //add by liyi
+//#define Mb_Dbuff_RL_SET_SINGLE_OUT_CH2       234		//add by liyi
+//#define Mb_Dbuff_RL_SET_SINGLE_OUT_CH3       235    //add by liyi
+//#define Mb_Dbuff_RL_SET_SINGLE_OUT_CH4       236    //add by liyi
 
 #define Mb_Dbuff_RL_Over_Ch1_Func    	240
 #define Mb_Dbuff_RL_Over_Ch2_Func    	241
@@ -247,6 +247,16 @@
 #define Mb_Dbuff_break_Addr					330
 #define Mb_Dbuff_Info_Addr          331
 
+#define Mb_Dbuff_Ch1_Ctrl_Addr       340
+#define Mb_Dbuff_Ch2_Ctrl_Addr       341
+#define Mb_Dbuff_Ch3_Ctrl_Addr       342
+#define Mb_Dbuff_Ch4_Ctrl_Addr       343
+#define Mb_Dbuff_Ch5_Ctrl_Addr       344
+#define Mb_Dbuff_Ch6_Ctrl_Addr       345
+#define Mb_Dbuff_Ch7_Ctrl_Addr       346
+#define Mb_Dbuff_Ch8_Ctrl_Addr       347
+#define Mb_Dbuff_Ch9_Ctrl_Addr       348
+
 
 
 
@@ -743,6 +753,16 @@
 #define AC3PPDU_INFOMATION                       (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Info_Addr)
 
 
+#define AC3PPDU_CH1_CTRL                         (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Ch1_Ctrl_Addr)							//add by liyi
+#define AC3PPDU_CH2_CTRL                         (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Ch2_Ctrl_Addr)							//add by liyi
+#define AC3PPDU_CH3_CTRL                         (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Ch3_Ctrl_Addr)							//add by liyi
+#define AC3PPDU_CH4_CTRL                         (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Ch4_Ctrl_Addr)							//add by liyi
+#define AC3PPDU_CH5_CTRL                         (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Ch5_Ctrl_Addr)							//add by liyi
+#define AC3PPDU_CH6_CTRL                         (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Ch6_Ctrl_Addr)							//add by liyi
+#define AC3PPDU_CH7_CTRL                         (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Ch7_Ctrl_Addr)							//add by liyi
+#define AC3PPDU_CH8_CTRL                         (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Ch8_Ctrl_Addr)							//add by liyi
+#define AC3PPDU_CH9_CTRL                         (AC3PPDU_Modbus_RegStAd + Mb_Dbuff_Ch9_Ctrl_Addr)							//add by liyi
+
 
 //Eeprom?????????????????????
 
@@ -1084,8 +1104,8 @@
 #define ERom_ALL_Over_Func_ByteN   	1														  // add by liyi
 
 
-#define ERom_SINGLE_OUT_CH_Addr     (ERom_RL_RegStAd + 400)
-#define ERom_SINGLE_OUT_CH_ByteN    (4)
+#define ERom_CH_CTRL_Addr     (ERom_RL_RegStAd + 400)
+#define ERom_CH_CTRL_ByteN    (10)