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@@ -28,6 +28,7 @@
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#include "ReadEeprom.h"
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#include "gd32e230x_conf.h"
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#include "Timer.h"
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+#include "Uart1.h"
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/* ----------------------- Defines ------------------------------------------*/
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//输入寄存器
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#define REG_INPUT_START 3000
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@@ -71,7 +72,6 @@ extern uint8_t RL_now_state;
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extern uint8_t AC3PPDU_SlaveAddress;
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extern uint32_t AC3PPDU_Modbus_Reg[AC3PPDU_Modbus_Reg_len];
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-extern AC3PPDU_RELAY_Para_Reg AC3PPDU_RL_time;
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/****************************************************************************
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* 名 称:eMBRegInputCB
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* 功 能:读取输入寄存器,对应功能码是 04 eMBFuncReadInputRegister
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@@ -127,6 +127,16 @@ eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs )
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unsigned char WusNRegs;
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unsigned int WiRegIndex;
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+extern void LimiT_enable_check(uint8_t ch_x,uint32_t Lt_v);
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+extern AC3PPDU_RELAY_Para_Reg AC3PPDU_RL_time[Output_ChN_default + 2];
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+extern AC3PPDU_RELAY_Para_Reg AC3PPDU_RL_N_time;
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+extern uint8_t OutUnit_control_flag[Output_ChN_default +1];
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+extern uint32_t hlw8110_base[Output_ChN_default + 1];
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+extern void channel_reset(uint8_t ch_x);
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+extern void hlw8110_init(uint8_t ch_x);
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+
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+extern uint8_t reset_hlw8110_flag[Output_ChN_default + 1];
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+
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eMBErrorCode
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eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode )
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{
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@@ -198,11 +208,329 @@ eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegi
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memcpy((Modbus_Wr_buff[cmd_cnt]+2),&usRegHoldBuf[WiRegIndex],WusNRegs * 2);
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Modbus_Wr_buff[cmd_cnt][0] = 1;
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Modbus_Wr_buff[cmd_cnt][1] = T_cnt;
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+ uint32_t temp_addr;
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+ uint32_t base_addr = Modbus_Wr_buff[cmd_cnt][1];
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+ uint32_t data = Modbus_Wr_buff[cmd_cnt][2];
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+
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+ switch(T_cnt)
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+ {
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+// case Mb_Dbuff_ViLit_max_Addr ... Mb_Dbuff_kWhiLit_max_Addr: //input votage max votage min current power coustermer add by liyi
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_ViLit_max_Addr;
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+// temp_addr = temp_addr << 2;
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+// temp_addr += ERom_ViLit_max_Addr;
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+// Eeprom_Rbuf[temp_addr + 0] = data >> 24;
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+// Eeprom_Rbuf[temp_addr + 1] = data >> 16;
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+// Eeprom_Rbuf[temp_addr + 2] = data >> 8;
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+// Eeprom_Rbuf[temp_addr + 3] = data >> 0;
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+// AC3PPDU_Modbus_Reg[base_addr] = data;
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+// }
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+// break;
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+// case Mb_Dbuff_VLit1_max_Addr ... Mb_Dbuff_VLit9_max_Addr: //output voltage max threod for 1,2,3,4,5,6,7,8,9 channels
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_ViLit_max_Addr;
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+
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+// temp_addr = temp_addr << 2;
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+// temp_addr += ERom_VLit1_max_Addr;
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+// Eeprom_Rbuf[temp_addr + 0] = data >> 24;
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+// Eeprom_Rbuf[temp_addr + 1] = data >> 16;
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+// Eeprom_Rbuf[temp_addr + 2] = data >> 8;
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+// Eeprom_Rbuf[temp_addr + 3] = data >> 0;
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+// AC3PPDU_Modbus_Reg[base_addr] = data;
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+// if(AC3PPDU_Modbus_Reg[base_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// uint32_t value = base_addr - Mb_Dbuff_VLit1_max_Addr;
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+// AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Vmax_Threshould_Disable);
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+// LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
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+// }
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+// }
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+// break;
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+// case Mb_Dbuff_VLit1_min_Addr ... Mb_Dbuff_VLit9_min_Addr: //output voltage min thred for 1,2,3,4,5,6,7,8,9 channels
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_VLit1_min_Addr;
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+// temp_addr = temp_addr << 2;
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+// temp_addr += ERom_VLit1_min_Addr;
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+// Eeprom_Rbuf[temp_addr + 0] = data >> 24;
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+// Eeprom_Rbuf[temp_addr + 1] = data >> 16;
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+// Eeprom_Rbuf[temp_addr + 2] = data >> 8;
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+// Eeprom_Rbuf[temp_addr + 3] = data >> 0;
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+// AC3PPDU_Modbus_Reg[base_addr] = data;
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+// if(AC3PPDU_Modbus_Reg[base_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// uint32_t value = base_addr - Mb_Dbuff_VLit1_min_Addr;
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+// AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Vmin_Threshould_Disable);
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+// LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
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+// }
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+// }
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+// break;
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+// case Mb_Dbuff_ILit1_max_Addr ... Mb_Dbuff_ILit9_max_Addr: // output current max throud for 1,2,3,4,5,6,7,8,9 channels
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_ILit1_max_Addr;
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+// temp_addr = temp_addr << 2;
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+// temp_addr += ERom_ILit1_max_Addr;
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+// Eeprom_Rbuf[temp_addr + 0] = data >> 24;
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+// Eeprom_Rbuf[temp_addr + 1] = data >> 16;
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+// Eeprom_Rbuf[temp_addr + 2] = data >> 8;
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+// Eeprom_Rbuf[temp_addr + 3] = data >> 0;
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+// AC3PPDU_Modbus_Reg[base_addr] = data;
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+// if(AC3PPDU_Modbus_Reg[base_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// uint32_t value = base_addr - Mb_Dbuff_ILit1_max_Addr;
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+// AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Imax_Threshould_Disable);
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+// LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
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+// }
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+// }
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+// break;
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+// case Mb_Dbuff_WLit1_max_Addr ... Mb_Dbuff_WLit9_max_Addr:
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_WLit1_max_Addr;
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+//// value = temp_addr;
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+// temp_addr = temp_addr << 2;
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+// temp_addr += ERom_WLit1_max_Addr;
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+// Eeprom_Rbuf[temp_addr + 0] = data >> 24;
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+// Eeprom_Rbuf[temp_addr + 1] = data >> 16;
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+// Eeprom_Rbuf[temp_addr + 2] = data >> 8;
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+// Eeprom_Rbuf[temp_addr + 3] = data >> 0;
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+// AC3PPDU_Modbus_Reg[base_addr] = data;
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+// if(AC3PPDU_Modbus_Reg[base_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// uint32_t value = base_addr - Mb_Dbuff_WLit1_max_Addr;
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+// AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Wmax_Threshould_Disable);
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+// LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
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+// }
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+// }
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+// break;
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+// case Mb_Dbuff_kWhLit1_max_Addr ... Mb_Dbuff_kWhLit9_max_Addr:
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_kWhLit1_max_Addr;
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+// //value = temp_addr;
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+// temp_addr = temp_addr << 2;
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+// temp_addr += ERom_kWhLit1_max_Addr;
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+// Eeprom_Rbuf[temp_addr + 0] = data >> 24;
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+// Eeprom_Rbuf[temp_addr + 1] = data >> 16;
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+// Eeprom_Rbuf[temp_addr + 2] = data >> 8;
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+// Eeprom_Rbuf[temp_addr + 3] = data >> 0;
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+// AC3PPDU_Modbus_Reg[base_addr] = data;
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+// if(AC3PPDU_Modbus_Reg[base_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// uint32_t value = base_addr - Mb_Dbuff_kWhLit1_max_Addr;
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+// AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Wmax_Threshould_Disable);
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+// LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
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+// }
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+// }
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+// break;
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+// case Mb_Dbuff_RL_Allon_Addr:
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+// {
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+// //RL_Allon_flag = true;
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+// for(int i = 0;i < Output_ChN_default;i++)
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+// {
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+// temp_addr = i << 1;
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+// Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
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+// AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
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+// }
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+// Eeprom_Rbuf[ERom_CHNLT_ST_Addr] = Eeprom_Rbuf[ERom_CHNLT_ST_Addr] | 0x41;
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+// AC3PPDU_RL_N_time.LT_state = Eeprom_Rbuf[ERom_CHNLT_ST_Addr];
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+// }
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+// break;
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+// case Mb_Dbuff_RL_Alloff_Addr:
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+// {
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+// //RL_Alloff_flag = true;
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+// for(int i = 0;i < Output_ChN_default;i++)
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+// {
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+// temp_addr = i << 1;
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+// Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
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+// Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
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+// AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
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+// }
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+// Eeprom_Rbuf[ERom_CHNLT_ST_Addr] = Eeprom_Rbuf[ERom_CHNLT_ST_Addr] | 0x80;
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+// Eeprom_Rbuf[ERom_CHNLT_ST_Addr] = Eeprom_Rbuf[ERom_CHNLT_ST_Addr] & 0xfe;
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+// AC3PPDU_RL_N_time.LT_state = Eeprom_Rbuf[ERom_CHNLT_ST_Addr];
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+// }
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+// break;
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+// case Mb_Dbuff_LT_ST_Addr: //set input status
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+// {
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+// AC3PPDU_RL_time[CH_in].LT_state = data;
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+// Eeprom_Rbuf[ERom_LT_ST_Addr] = data;
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+// AC3PPDU_Modbus_Reg[base_addr] = data;
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+// LimiT_enable_check(CH_in,AC3PPDU_RL_time[CH_in].LT_state);
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+// }
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+// break;
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+// case Mb_Dbuff_CH1LT_ST_Addr ... Mb_Dbuff_CHNLT_ST_Addr: //set output relay statues
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_CH1LT_ST_Addr;
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+// if(temp_addr == 9) { //Ch N
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+// AC3PPDU_RL_N_time.LT_state = data;
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+// }else{
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Vmax_Threshould_Disable);
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+// }
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Vmin_Threshould_Disable);
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+// }
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Imax_Threshould_Disable);
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+// }
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Wmax_Threshould_Disable);
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+// }
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Kwhmax_Threshould_Disable);
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+// }
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+//
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+// AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
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+// LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
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+// }
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+// temp_addr = temp_addr << 1;
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+// temp_addr += ERom_CH1LT_ST_Addr;
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+// Eeprom_Rbuf[temp_addr] = data;
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+// }
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+// break;
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+// case Mb_Dbuff_OUTCH1_ST_Addr ... Mb_Dbuff_OUTCH3_ST_Addr: //set output channel relay's status
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_OUTCH1_ST_Addr;
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+// OutUnit_control_flag[temp_addr] = 1;
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+// temp_addr *= 3;
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Vmax_Threshould_Disable);
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+// }
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Vmin_Threshould_Disable);
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+// }
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Imax_Threshould_Disable);
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+// }
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Wmax_Threshould_Disable);
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+// }
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+// if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + temp_addr] < THRESHOULD_JUDGMENT)
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+// {
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+// data &= (Shield_Kwhmax_Threshould_Disable);
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+// }
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+//
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+// AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
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+// AC3PPDU_RL_time[temp_addr + CH2_out].LT_state = data;
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+// AC3PPDU_RL_time[temp_addr + CH3_out].LT_state = data;
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+//
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+// temp_addr = temp_addr << 1;
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+// Eeprom_Rbuf[temp_addr + ERom_CH1LT_ST_Addr] = data;
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+// Eeprom_Rbuf[temp_addr + ERom_CH2LT_ST_Addr] = data;
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+// Eeprom_Rbuf[temp_addr + ERom_CH3LT_ST_Addr] = data;
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+//
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+// LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
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+// LimiT_enable_check((temp_addr + CH2_out),AC3PPDU_RL_time[temp_addr + CH2_out].LT_state);
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+// LimiT_enable_check((temp_addr + CH3_out),AC3PPDU_RL_time[temp_addr + CH3_out].LT_state);
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+//
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+// }
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+// break;
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+// case Mb_Dbuff_RL_Ton1_Addr ... Mb_Dbuff_RL_TonN_Addr: //set on status delay for 1,2,3,4,5,6,7,8,9,N channels
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_RL_Ton1_Addr;
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+// if(temp_addr == 9){ //Ch N add by liyi
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+// AC3PPDU_RL_N_time.RL_ontime = data;
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+// }else
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+// {
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+// AC3PPDU_RL_time[temp_addr + CH1_out].RL_ontime = data;
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+// }
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+// AC3PPDU_RL_N_time.RL_ontime = data;
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+// temp_addr += ERom_RL_Ton1_Addr;
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+//
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+// Eeprom_Rbuf[temp_addr] = data;
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+// Eeprom_Rbuf[ERom_RL_TonN_Addr] = data;
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+// AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
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+// AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_TonN_Addr] = Eeprom_Rbuf[ERom_RL_TonN_Addr];
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+// }
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+// break;
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+// case Mb_Dbuff_RL_Toff1_Addr ... Mb_Dbuff_RL_ToffN_Addr: //set off status delay for 1,2,3,4,5,6,7,8,9,N channels
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+// {
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+// temp_addr = base_addr - Mb_Dbuff_RL_Toff1_Addr;
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+// if(temp_addr == 9){
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+// AC3PPDU_RL_N_time.RL_offtime = data;
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+// }else {
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+// AC3PPDU_RL_time[temp_addr + CH1_out].RL_offtime = data;
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+// }
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+// AC3PPDU_RL_N_time.RL_offtime = data;
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+// temp_addr += ERom_RL_Toff1_Addr;
|
|
|
+//
|
|
|
+// Eeprom_Rbuf[temp_addr] = data;
|
|
|
+// Eeprom_Rbuf[ERom_RL_ToffN_Addr] = data;
|
|
|
+// AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
|
|
|
+// AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_ToffN_Addr] = Eeprom_Rbuf[ERom_RL_ToffN_Addr];
|
|
|
+// }
|
|
|
+// break;
|
|
|
+// case Mb_Dbuff_RL_Over_Ch1_Func ... Mb_Dbuff_RL_Over_Ch9_Func: //threod over limit operation
|
|
|
+// {
|
|
|
+// temp_addr = base_addr - Mb_Dbuff_RL_Over_Ch1_Func;
|
|
|
+// temp_addr += ERom_RL_Over_Ch1_Addr;
|
|
|
+// AC3PPDU_Modbus_Reg[base_addr] = data;
|
|
|
+// Eeprom_Rbuf[temp_addr] = data;
|
|
|
+// }
|
|
|
+// break;
|
|
|
+ case Mb_Dbuff_Clear_Chn1_Consumer ... Mb_Dbuff_Clear_Chn9_Consumer:
|
|
|
+ {
|
|
|
+ if(data)
|
|
|
+ {
|
|
|
+ temp_addr = base_addr - Mb_Dbuff_Clear_Chn1_Consumer;
|
|
|
+ int value = temp_addr;
|
|
|
+ //Hlw8110_Flash_value[temp_addr+CH1_out] = AC3PPDU_Output[temp_addr+CH1_out].AC_kWh;
|
|
|
+ //Hlw8110_Flash_value[temp_addr+CH1_out] = Hlw8110_Flash_Backup[temp_addr+CH1_out];
|
|
|
+ hlw8110_base[temp_addr+CH1_out] = 0;
|
|
|
+ temp_addr = temp_addr << 2;
|
|
|
+ temp_addr += ERom_TotalWh1_Addr;
|
|
|
+ Eeprom_Rbuf[temp_addr+0] = 0;
|
|
|
+ Eeprom_Rbuf[temp_addr+1] = 0;
|
|
|
+ Eeprom_Rbuf[temp_addr+2] = 0;
|
|
|
+ Eeprom_Rbuf[temp_addr+3] = 0;
|
|
|
+ channel_reset(value+CH1_out);
|
|
|
+ InitUART1(9600);
|
|
|
+ reset_hlw8110_flag[value] =1;
|
|
|
+ //hlw8110_init(value+CH1_out);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ case Mb_Dbuff_Clear_Chnall_Consumer:
|
|
|
+ {
|
|
|
+ if(data)
|
|
|
+ {
|
|
|
+ for(int i = 0; i < Output_ChN_default ;i++)
|
|
|
+ {
|
|
|
+ int temp = i << 2;
|
|
|
+ //Hlw8110_Flash_value[i+CH1_out] = AC3PPDU_Output[i+CH1_out].AC_kWh;
|
|
|
+ //Hlw8110_Flash_value[i+CH1_out] = Hlw8110_Flash_Backup[i+CH1_out];
|
|
|
+ Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+0] = 0;
|
|
|
+ Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+1] = 0;
|
|
|
+ Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+2] = 0;
|
|
|
+ Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+3] = 0;
|
|
|
+ hlw8110_base[i+CH1_out] = 0;
|
|
|
+ channel_reset(i+CH1_out);
|
|
|
+ reset_hlw8110_flag[i] = 0;
|
|
|
+ }
|
|
|
+ InitUART1(9600);
|
|
|
+ //InitCH448F();
|
|
|
+// for(int i = 0; i < Output_ChN_default ;i++)
|
|
|
+// hlw8110_init(i+CH1_out);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
cmd_cnt++;
|
|
|
if(cmd_cnt >= Mb_Wcmd_Width)
|
|
|
{
|
|
|
cmd_cnt = 0;
|
|
|
}
|
|
|
+
|
|
|
}
|
|
|
}
|
|
|
else//错误
|