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@@ -92,7 +92,7 @@ META_DATA_S meta_data = {0};
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uint8_t write_kwh2Eeprom_flag = 0;
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uint8_t write_kwh2Eeprom_flag = 0;
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-#if SUPPORT_DETECT_REMENBER
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+
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uint8_t handle_status[Output_ChN_default] = {0};
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uint8_t handle_status[Output_ChN_default] = {0};
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#if SUPPORT_DOUBLE_FIRE
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#if SUPPORT_DOUBLE_FIRE
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@@ -103,7 +103,7 @@ uint8_t write_kwh2Eeprom_flag = 0;
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#if SUPPORT_ZERO_LINE
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#if SUPPORT_ZERO_LINE
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uint8_t handle_status_N = 0;
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uint8_t handle_status_N = 0;
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#endif
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#endif
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-#endif
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+
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@@ -585,6 +585,14 @@ void switch_recode()
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AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state &= 0xffffff7e;
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AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state &= 0xffffff7e;
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orderFlag[i+PH_STEP]=true;
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orderFlag[i+PH_STEP]=true;
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sync_buff[i] = 1;
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sync_buff[i] = 1;
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+ }else
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+ {
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+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
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+ {
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+ handle_status[i] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
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+ AC3PPDU_RL_time[i + CH1_out].LT_state &= 0xffffff7e;
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+ orderFlag[i]=true;
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+ }
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}
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}
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}
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}
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handle_detection[0] = 0;
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handle_detection[0] = 0;
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@@ -610,6 +618,14 @@ void switch_recode()
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AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state &= 0xffffff7e;
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AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state &= 0xffffff7e;
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orderFlag[i+PH_STEP]=true;
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orderFlag[i+PH_STEP]=true;
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}
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}
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+ }else
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+ {
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+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
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+ {
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+ handle_status[i+PH_STEP] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i +PH_STEP] & 0x1);
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+ AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state &= 0xffffff7e;
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+ orderFlag[i+PH_STEP]=true;
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+ }
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}
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}
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}
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}
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handle_detection[1] = 0;
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handle_detection[1] = 0;
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@@ -631,6 +647,14 @@ void switch_recode()
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AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state |= handle_status[i+PH_STEP];
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AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state |= handle_status[i+PH_STEP];
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orderFlag[i+PH_STEP]=true;
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orderFlag[i+PH_STEP]=true;
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sync_buff[i] = 1;
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sync_buff[i] = 1;
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+ }else
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+ {
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+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
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+ {
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+ AC3PPDU_RL_time[i + CH1_out].LT_state |= 0x40;
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+ AC3PPDU_RL_time[i + CH1_out].LT_state |= handle_status[i];
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+ orderFlag[i]=true;
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+ }
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}
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}
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}
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}
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}
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}
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@@ -653,6 +677,14 @@ void switch_recode()
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AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state |= handle_status[i+PH_STEP];
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AC3PPDU_RL_time[i + CH1_out + PH_STEP].LT_state |= handle_status[i+PH_STEP];
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orderFlag[i+PH_STEP]=true;
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orderFlag[i+PH_STEP]=true;
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}
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}
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+ }else
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+ {
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+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+PH_STEP] == 0)
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+ {
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+ AC3PPDU_RL_time[i + CH1_out+PH_STEP].LT_state |= 0x40;
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+ AC3PPDU_RL_time[i + CH1_out+PH_STEP].LT_state |= handle_status[i+PH_STEP];
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+ orderFlag[i+PH_STEP]=true;
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+ }
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}
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}
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}
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}
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}
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}
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@@ -664,9 +696,12 @@ void switch_recode()
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{
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{
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for(int i = 0; i < Output_ChN_default;i++)
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for(int i = 0; i < Output_ChN_default;i++)
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{
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{
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- handle_status[i] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
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- AC3PPDU_RL_time[i + CH1_out].LT_state &= 0xffffff7e;
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- orderFlag[i]=true;
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+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
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+ {
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+ handle_status[i] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
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+ AC3PPDU_RL_time[i + CH1_out].LT_state &= 0xffffff7e;
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+ orderFlag[i]=true;
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+ }
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}
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}
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#if SUPPORT_ZERO_LINE
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#if SUPPORT_ZERO_LINE
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handle_status_N = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr] & 0x1);
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handle_status_N = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr] & 0x1);
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@@ -681,10 +716,13 @@ void switch_recode()
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{
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{
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for(int i = 0; i < Output_ChN_default;i++)
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for(int i = 0; i < Output_ChN_default;i++)
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{
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{
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- uint32_t data = (AC3PPDU_RL_time[i + CH1_out].LT_state & (~0x40));
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- AC3PPDU_RL_time[i + CH1_out].LT_state = (data & 0x40);
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- AC3PPDU_RL_time[i + CH1_out].LT_state |= handle_status[i];
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- orderFlag[i]=true;
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+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
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+ {
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+ uint32_t data = (AC3PPDU_RL_time[i + CH1_out].LT_state & (~0x40));
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+ AC3PPDU_RL_time[i + CH1_out].LT_state = (data & 0x40);
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+ AC3PPDU_RL_time[i + CH1_out].LT_state |= handle_status[i];
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+ orderFlag[i]=true;
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+ }
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}
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}
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#if SUPPORT_ZERO_LINE
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#if SUPPORT_ZERO_LINE
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uint32_t data = (AC3PPDU_RL_N_time.LT_state & (~0x40));
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uint32_t data = (AC3PPDU_RL_N_time.LT_state & (~0x40));
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@@ -899,26 +937,14 @@ int main(void)
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for(int i = 0; i < Output_ChN_default;i+=3)
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for(int i = 0; i < Output_ChN_default;i+=3)
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{
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{
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- if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
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+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+1] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+2] == 0)
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{
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{
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handle_status[i ] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
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handle_status[i ] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
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handle_status[i+1] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + 1] & 0x1);
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handle_status[i+1] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + 1] & 0x1);
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handle_status[i+2] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + 2] & 0x1);
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handle_status[i+2] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + 2] & 0x1);
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- }else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
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- {
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- handle_status[i ] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] & 0x1);
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- AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + 1] &= 0xfffffffe;
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- AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + 2] &= 0xfffffffe;
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- }else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
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- {
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- handle_status[i+1] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + 1] & 0x1);
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AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
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AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
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- AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + 2] &= 0xfffffffe;
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- }else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 3)
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- {
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- AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
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- AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i + 1] &= 0xfffffffe;
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- handle_status[i+2] = (AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i+2] & 0x1);
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+ AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i+1] &= 0xfffffffe;
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+ AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i+2] &= 0xfffffffe;
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}
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}
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}
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}
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@@ -1259,7 +1285,7 @@ static void MODbus_CMD_New(void)
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RL_Allon_flag = true;
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RL_Allon_flag = true;
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for(int i = 0; i < Output_ChN_default;i+=3)
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for(int i = 0; i < Output_ChN_default;i+=3)
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{
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{
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- if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0)
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+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+1] == 0 && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+2] == 0)
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{
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{
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temp_addr = i << 1;
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temp_addr = i << 1;
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Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
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Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
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@@ -1273,47 +1299,29 @@ static void MODbus_CMD_New(void)
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Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
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Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
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AC3PPDU_RL_time[i + CH1_out + 2].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
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AC3PPDU_RL_time[i + CH1_out + 2].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
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orderFlag[i+2]=true;
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orderFlag[i+2]=true;
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- }else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
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- {
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- temp_addr = i << 1;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
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- AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
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- orderFlag[i]=true;
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-
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- temp_addr = (i+1) << 1;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
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-
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- temp_addr = (i+2) << 1;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
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-
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- }else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
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+ }else
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{
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{
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- temp_addr = (i+1) << 1;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
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- AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
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- orderFlag[i+1]=true;
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-
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- temp_addr = (i) << 1;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
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-
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- temp_addr = (i+2) << 1;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
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- }else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 3)
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- {
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- temp_addr = (i) << 1;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
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- temp_addr = (i+1) << 1;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
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- temp_addr = (i+2) << 1;
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- Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
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- AC3PPDU_RL_time[i + CH1_out + 2].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
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- orderFlag[i+2]=true;
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+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
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+ {
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+ temp_addr = i << 1;
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+ Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
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+ AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
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+ orderFlag[i]=true;
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+ }
|
|
|
|
|
+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+1] == 0)
|
|
|
|
|
+ {
|
|
|
|
|
+ temp_addr = (i+1) << 1;
|
|
|
|
|
+ Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
|
|
|
|
|
+ AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
|
|
|
|
|
+ orderFlag[i+1]=true;
|
|
|
|
|
+ }
|
|
|
|
|
+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i+2] == 0)
|
|
|
|
|
+ {
|
|
|
|
|
+ temp_addr = (i+2) << 1;
|
|
|
|
|
+ Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
|
|
|
|
|
+ AC3PPDU_RL_time[i + CH1_out + 2].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
|
|
|
|
|
+ orderFlag[i+2]=true;
|
|
|
|
|
+ }
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
// for(i = 0;i < Output_ChN_default;i++)
|
|
// for(i = 0;i < Output_ChN_default;i++)
|
|
@@ -1480,9 +1488,9 @@ static void MODbus_CMD_New(void)
|
|
|
#else
|
|
#else
|
|
|
if(detection_value == 1)
|
|
if(detection_value == 1)
|
|
|
{
|
|
{
|
|
|
- for(int i = 0; i < Output_ChN_default;i+=3)
|
|
|
|
|
|
|
+ for(int i = 0; i < Output_ChN_default;i++)
|
|
|
{
|
|
{
|
|
|
- if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 0 || AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 1)
|
|
|
|
|
|
|
+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+i] == 0)
|
|
|
{
|
|
{
|
|
|
if(temp_addr == i)
|
|
if(temp_addr == i)
|
|
|
{
|
|
{
|
|
@@ -1495,35 +1503,8 @@ static void MODbus_CMD_New(void)
|
|
|
AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
|
|
AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
|
|
|
break;
|
|
break;
|
|
|
}
|
|
}
|
|
|
- }else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 2)
|
|
|
|
|
- {
|
|
|
|
|
- if(temp_addr == (i+1))
|
|
|
|
|
- {
|
|
|
|
|
- AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
|
|
|
|
|
- orderFlag[temp_addr]=true;
|
|
|
|
|
- LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
|
|
|
|
|
- temp_addr = temp_addr << 1;
|
|
|
|
|
- temp_addr += ERom_CH1LT_ST_Addr;
|
|
|
|
|
- Eeprom_Rbuf[temp_addr] = data;
|
|
|
|
|
- AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
|
|
|
|
|
- break;
|
|
|
|
|
- }
|
|
|
|
|
- }else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_SET_SINGLE_OUT_CH1+i] == 3)
|
|
|
|
|
- {
|
|
|
|
|
- if(temp_addr == (i+2))
|
|
|
|
|
- {
|
|
|
|
|
- AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
|
|
|
|
|
- orderFlag[temp_addr]=true;
|
|
|
|
|
- LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
|
|
|
|
|
- temp_addr = temp_addr << 1;
|
|
|
|
|
- temp_addr += ERom_CH1LT_ST_Addr;
|
|
|
|
|
- Eeprom_Rbuf[temp_addr] = data;
|
|
|
|
|
- AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
|
|
|
|
|
- break;
|
|
|
|
|
- }
|
|
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
}
|
|
}
|
|
|
#endif
|
|
#endif
|
|
|
#endif
|
|
#endif
|
|
@@ -1593,48 +1574,52 @@ static void MODbus_CMD_New(void)
|
|
|
temp_addr = base_addr - Mb_Dbuff_OUTCH1_ST_Addr;
|
|
temp_addr = base_addr - Mb_Dbuff_OUTCH1_ST_Addr;
|
|
|
//OutUnit_control_flag[temp_addr] = 1;
|
|
//OutUnit_control_flag[temp_addr] = 1;
|
|
|
temp_addr *= 3;
|
|
temp_addr *= 3;
|
|
|
- if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
- {
|
|
|
|
|
- data &= (Shield_Vmax_Threshould_Disable);
|
|
|
|
|
- }
|
|
|
|
|
- if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
- {
|
|
|
|
|
- data &= (Shield_Vmin_Threshould_Disable);
|
|
|
|
|
- }
|
|
|
|
|
- if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
- {
|
|
|
|
|
- data &= (Shield_Imax_Threshould_Disable);
|
|
|
|
|
- }
|
|
|
|
|
- if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
- {
|
|
|
|
|
- data &= (Shield_Wmax_Threshould_Disable);
|
|
|
|
|
- }
|
|
|
|
|
- if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
- {
|
|
|
|
|
- data &= (Shield_Kwhmax_Threshould_Disable);
|
|
|
|
|
- }
|
|
|
|
|
-
|
|
|
|
|
- AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
|
|
|
|
|
- AC3PPDU_RL_time[temp_addr + CH2_out].LT_state = data;
|
|
|
|
|
- AC3PPDU_RL_time[temp_addr + CH3_out].LT_state = data;
|
|
|
|
|
- for(int i=0;i<Output_ChN_default;i++)
|
|
|
|
|
|
|
+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+temp_addr] == 0
|
|
|
|
|
+ && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+temp_addr+1] == 0
|
|
|
|
|
+ && AC3PPDU_Modbus_Reg[Mb_Dbuff_Ch1_Ctrl_Addr+temp_addr+2] == 0)
|
|
|
{
|
|
{
|
|
|
- orderFlag[i]=true;
|
|
|
|
|
|
|
+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
+ {
|
|
|
|
|
+ data &= (Shield_Vmax_Threshould_Disable);
|
|
|
|
|
+ }
|
|
|
|
|
+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
+ {
|
|
|
|
|
+ data &= (Shield_Vmin_Threshould_Disable);
|
|
|
|
|
+ }
|
|
|
|
|
+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
+ {
|
|
|
|
|
+ data &= (Shield_Imax_Threshould_Disable);
|
|
|
|
|
+ }
|
|
|
|
|
+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
+ {
|
|
|
|
|
+ data &= (Shield_Wmax_Threshould_Disable);
|
|
|
|
|
+ }
|
|
|
|
|
+ if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
|
|
|
|
|
+ {
|
|
|
|
|
+ data &= (Shield_Kwhmax_Threshould_Disable);
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
|
|
|
|
|
+ AC3PPDU_RL_time[temp_addr + CH2_out].LT_state = data;
|
|
|
|
|
+ AC3PPDU_RL_time[temp_addr + CH3_out].LT_state = data;
|
|
|
|
|
+ for(int i=0;i<Output_ChN_default;i++)
|
|
|
|
|
+ {
|
|
|
|
|
+ orderFlag[i]=true;
|
|
|
|
|
+ }
|
|
|
|
|
+ //orderFlag_N = true;
|
|
|
|
|
+ LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
|
|
|
|
|
+ LimiT_enable_check((temp_addr + CH2_out),AC3PPDU_RL_time[temp_addr + CH2_out].LT_state);
|
|
|
|
|
+ LimiT_enable_check((temp_addr + CH3_out),AC3PPDU_RL_time[temp_addr + CH3_out].LT_state);
|
|
|
|
|
+
|
|
|
|
|
+ temp_addr = temp_addr << 1;
|
|
|
|
|
+ Eeprom_Rbuf[temp_addr + ERom_CH1LT_ST_Addr] = data;
|
|
|
|
|
+ Eeprom_Rbuf[temp_addr + ERom_CH2LT_ST_Addr] = data;
|
|
|
|
|
+ Eeprom_Rbuf[temp_addr + ERom_CH3LT_ST_Addr] = data;
|
|
|
|
|
+
|
|
|
|
|
+ AT24CxxWriteOneByte(temp_addr + ERom_CH1LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH1LT_ST_Addr]);
|
|
|
|
|
+ AT24CxxWriteOneByte(temp_addr + ERom_CH2LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH2LT_ST_Addr]);
|
|
|
|
|
+ AT24CxxWriteOneByte(temp_addr + ERom_CH3LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH3LT_ST_Addr]);
|
|
|
}
|
|
}
|
|
|
- //orderFlag_N = true;
|
|
|
|
|
- LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
|
|
|
|
|
- LimiT_enable_check((temp_addr + CH2_out),AC3PPDU_RL_time[temp_addr + CH2_out].LT_state);
|
|
|
|
|
- LimiT_enable_check((temp_addr + CH3_out),AC3PPDU_RL_time[temp_addr + CH3_out].LT_state);
|
|
|
|
|
-
|
|
|
|
|
- temp_addr = temp_addr << 1;
|
|
|
|
|
- Eeprom_Rbuf[temp_addr + ERom_CH1LT_ST_Addr] = data;
|
|
|
|
|
- Eeprom_Rbuf[temp_addr + ERom_CH2LT_ST_Addr] = data;
|
|
|
|
|
- Eeprom_Rbuf[temp_addr + ERom_CH3LT_ST_Addr] = data;
|
|
|
|
|
-
|
|
|
|
|
- AT24CxxWriteOneByte(temp_addr + ERom_CH1LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH1LT_ST_Addr]);
|
|
|
|
|
- AT24CxxWriteOneByte(temp_addr + ERom_CH2LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH2LT_ST_Addr]);
|
|
|
|
|
- AT24CxxWriteOneByte(temp_addr + ERom_CH3LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH3LT_ST_Addr]);
|
|
|
|
|
-
|
|
|
|
|
}
|
|
}
|
|
|
#endif
|
|
#endif
|
|
|
}
|
|
}
|