main.c 52 KB

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  1. #include "gd32e23x.h"
  2. #include "systick.h"
  3. #include <stdio.h>
  4. #include "main.h"
  5. #include "Fwdgt.h"
  6. #include "mb.h"
  7. #include "Led.h"
  8. #include "Key.h"
  9. #include "cfg.h"
  10. #include "gd32e23x_fmc.h"
  11. #include "string.h"
  12. #include "Timer.h"
  13. #include "Fwdgt.h"
  14. #include "stdbool.h"
  15. #include "At24cxx.h"
  16. #include "Sn74hc573.h"
  17. #include "Relay.h"
  18. #include "ReadEeprom.h"
  19. #include "Uart1.h"
  20. #include "Hlw8110.h"
  21. #include "key_io.h"
  22. AC_Output_struct_Reg AC3PPDU_Output[Output_ChN_default + 2] = {0};
  23. AC3PPDU_RELAY_Para_Reg AC3PPDU_RL_time[Output_ChN_default + 2] = {0};
  24. AC3PPDU_RELAY_Para_Reg AC3PPDU_RL_N_time;
  25. static uint8_t AC3PPDU_SlaveAddress = 0x00;
  26. uint16_t Devid_IDChalNum = 0;
  27. bool RL_Allon_flag = false;
  28. bool RL_Alloff_flag = false;
  29. bool Start_Read_Flag = false;
  30. uint16_t CurrentAddr = 0;
  31. uint8_t flash_flag = 0;
  32. uint32_t AC3PPDU_Modbus_Reg[AC3PPDU_Modbus_Reg_len] = {0};
  33. uint8_t AC3PPDU_active_chn;
  34. information_t infomation;
  35. uint32_t hlw8110_base[Output_ChN_default + 1] = {0}; //add by liyi
  36. uint8_t Wr_eeprom_cnt = 0;
  37. uint8_t RL_begin_delay_flag[Output_ChN_default+1] = {0x00};
  38. uint8_t RL_end_delay_flag[Output_ChN_default+1] = {0x00};
  39. uint8_t RL_ON_flag[Output_ChN_default+1] = {0x00};
  40. uint8_t RL_OFF_flag[Output_ChN_default+1] = {0x00};
  41. uint8_t RL_last_state[Output_ChN_default+1] = {0x00};
  42. uint8_t RL_now_state[Output_ChN_default+1] = {0x00};
  43. uint8_t RL_Func_statu[Output_ChN_default + 1] = {0x00};
  44. uint8_t RL_All_Func = 0x0;
  45. uint32_t normal_running_time = 0;
  46. uint8_t RL_N_begin_delay_flag = 0x0; // add by liyi
  47. uint8_t RL_N_end_delay_flag = 0x0; // add by liyi
  48. uint8_t RL_N_ON_flag = 0x0; // add by liyi
  49. uint8_t RL_N_OFF_flag = 0x0; // add by liyi
  50. uint8_t RL_N_last_state = 0x0; // add by liyi
  51. uint8_t RL_N_now_state = 0x0; // add by liyi
  52. uint8_t AC3PPDU_Vmax_LTen_flag[Output_ChN_default+1] = {0x01};
  53. uint8_t AC3PPDU_Vmin_LTen_flag[Output_ChN_default+1] = {0x01};
  54. uint8_t AC3PPDU_Imax_LTen_flag[Output_ChN_default+1] = {0x01};
  55. uint8_t AC3PPDU_Wmax_LTen_flag[Output_ChN_default+1] = {0x01};
  56. uint8_t AC3PPDU_kWhmax_LTen_flag[Output_ChN_default+1] = {0x01};
  57. uint32_t AC_BASE[4] = {0};
  58. META_DATA_S meta_data = {0};
  59. uint8_t write_kwh2Eeprom_flag = 0;
  60. extern float hlw8110_store[Output_ChN_default + 1];
  61. extern uint32_t Modbus_Wr_buff[Mb_Wcmd_Width][Mb_Wcmd_len];
  62. extern uint32_t RL_N_delay_cnt; // add by liyi
  63. extern uint32_t RL_N_delay_Limit; // add by liyi
  64. extern uint32_t RL_delay_Limit[Output_ChN_default + 1];
  65. static void MODbus_CMD_New(void);
  66. static void Fault_state_process(uint8_t ch_x);
  67. void flash_erase_meta()
  68. {
  69. fmc_unlock();
  70. fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGERR);
  71. fmc_page_erase(META_DATA);
  72. fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGERR);
  73. fmc_lock();
  74. }
  75. void flash_write_meta(const META_DATA_S *meta_data)
  76. {
  77. fmc_unlock();
  78. uint32_t address = META_DATA;
  79. uint32_t *data = (uint32_t*)(meta_data);
  80. uint32_t data0 = 0;
  81. for(int i = 0; i < sizeof(META_DATA_S);i++)
  82. {
  83. data0 = *data;
  84. fmc_word_program(address,data0);
  85. data ++;
  86. fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR | FMC_FLAG_PGERR);
  87. address +=4;
  88. }
  89. fmc_lock();
  90. }
  91. static void break_2_boot_upgreade(void)
  92. {
  93. meta_data.errno = 0;
  94. meta_data.operation_flag = 1;
  95. meta_data.recent_running_time = normal_running_time;
  96. flash_erase_meta();
  97. flash_write_meta(&meta_data);
  98. __disable_irq();
  99. //__set_FAULTMASK(1);
  100. NVIC_SystemReset();
  101. }
  102. void get_meta_data_from_flash(META_DATA_S *meta)
  103. {
  104. meta->operation_flag = *(uint32_t*)(UPGRADE_FLAG_ADDR);
  105. meta->partition = *(uint32_t*)(STARTUP_PARTATION);
  106. meta->errno = *(uint32_t*)(STARTUP_ERROR);
  107. meta->error_count = *(uint32_t*)(STARTUP_NUMBEAR);
  108. meta->rom_addr = *(uint32_t*)(STARTUP_ROM_ADDR);
  109. meta->recent_running_time = *(uint32_t*)(STARTUP_LAST_RUNNING_TIME);
  110. meta->running_app_version = *(uint32_t*)(STARTUP_APP_VERSION);
  111. meta->app1_version = *(uint32_t*)(APP1_VERSION);
  112. meta->app1_rom_addr = *(uint32_t*)(APP1_ROM_ADDR);
  113. meta->app1_partition = *(uint32_t*)(APP1_PARTATION);
  114. meta->app2_version = *(uint32_t*)(APP2_VERSION);
  115. meta->app2_rom_addr = *(uint32_t*)(APP2_ROM_ADDR);
  116. meta->app2_partition = *(uint32_t*)(APP2_PARTATION);
  117. uint32_t buff[MD5_LENTH] = {0};
  118. uint32_t addr = APP1_MD5;
  119. for(int i = 0;i < MD5_LENTH;i++)
  120. {
  121. buff[i] = *(uint32_t*)(addr);
  122. addr += 4;
  123. }
  124. memcpy(&meta->app1_md5[0],buff,sizeof(uint32_t) *MD5_LENTH);
  125. addr = APP2_MD5;
  126. for(int i = 0;i < MD5_LENTH;i++)
  127. {
  128. buff[i] = *(uint32_t*)(addr);
  129. addr += 4;
  130. }
  131. memcpy(&meta->app2_md5[0],buff,sizeof(uint32_t) *MD5_LENTH);
  132. meta->app1_size = *(uint32_t*)(APP1_SIZE);
  133. meta->app2_size = *(uint32_t*)(APP2_SIZE);
  134. }
  135. void flash_get_infomation(information_t *info)
  136. {
  137. info->uniq_ID_64_95 = *(uint32_t*)(UNIQU_3);
  138. info->uniq_ID_32_63 = *(uint32_t*)(UNIQU_2);
  139. info->uniq_ID_00_31 = *(uint32_t*)(UNIQU_1);
  140. }
  141. static void app_init(META_DATA_S *meta)
  142. {
  143. get_meta_data_from_flash(meta);
  144. nvic_vector_table_set(NVIC_VECTTAB_FLASH,meta->rom_addr - NVIC_VECTTAB_FLASH);
  145. __enable_irq();
  146. }
  147. static bool select_channel(uint8_t ch_x)
  148. {
  149. if(ch_x == 0)
  150. return false;
  151. switch(ch_x)
  152. {
  153. case CH1_out:
  154. {
  155. SEL_0_H;
  156. SEL_1_H;
  157. SEL_2_H;
  158. }
  159. break;
  160. case CH2_out:
  161. {
  162. SEL_0_L;
  163. SEL_1_H;
  164. SEL_2_H;
  165. }
  166. break;
  167. case CH3_out:
  168. {
  169. SEL_0_H;
  170. SEL_1_L;
  171. SEL_2_H;
  172. }
  173. break;
  174. default:
  175. return false;
  176. }
  177. return true;
  178. }
  179. void hlw8110_init(uint8_t ch_x)
  180. {
  181. if(select_channel(ch_x) == false)
  182. return;
  183. Init_HLW8110();
  184. }
  185. static void CHK_JLINK(void)
  186. {
  187. uint8_t i = 0;
  188. uint8_t j = 0;
  189. uint8_t temp0 = 0;
  190. uint8_t t_RL_state = 0;
  191. if(Chk_Jlink_conn() == false)//如果有jlink接入,则不会动作继电器,直接跳出进入主函数
  192. {
  193. //if(Fault_lack_phase_flag == false)//无缺相故障才能操作继电器
  194. {
  195. // DB_Out1_H;
  196. // DB_Out2_H;
  197. // DB_Out3_H;
  198. // DB_Out4_H ;
  199. // delay_ms(100);
  200. // DB_Out1_L;
  201. // DB_Out2_L;
  202. // DB_Out3_L;
  203. // DB_Out4_L;
  204. //
  205. // BUFF_Data;
  206. // LOCK_Data;
  207. // Ch N
  208. RL_N_now_state = AC3PPDU_RL_N_time.LT_state & 0x01;
  209. if(RL_N_now_state != RL_N_last_state)
  210. {
  211. if(RL_N_now_state > 0) { //open
  212. RL_N_ON_flag = 1; // Ch N open flag
  213. RL_N_OFF_flag = 0;
  214. if((AC3PPDU_RL_N_time.LT_state & 0x40) > 0){ // Ch N have delay
  215. RL_N_begin_delay_flag = 1;
  216. RL_N_end_delay_flag = 0;
  217. RL_N_delay_Limit = AC3PPDU_RL_N_time.RL_ontime * 1000; // exchange to ms
  218. }else {
  219. RL_N_begin_delay_flag = 0;
  220. RL_N_end_delay_flag = 1;
  221. RL_N_delay_Limit = 0;
  222. }
  223. }else { //close
  224. RL_N_ON_flag = 0;
  225. RL_N_OFF_flag = 1; // Ch N close flag
  226. if((AC3PPDU_RL_N_time.LT_state & 0x80) > 0)//有延时
  227. {
  228. RL_N_begin_delay_flag = 1;
  229. RL_N_end_delay_flag = 0;
  230. RL_N_delay_Limit = AC3PPDU_RL_N_time.RL_offtime * 1000;//秒转成毫秒
  231. }
  232. else//无延时
  233. {
  234. RL_N_begin_delay_flag = 0;
  235. RL_N_end_delay_flag = 1;
  236. RL_N_delay_Limit = 0;
  237. }
  238. }
  239. RL_N_last_state = RL_N_now_state;
  240. }else{
  241. //OutUnit_N_control_flag = 0;
  242. }
  243. if(RL_N_end_delay_flag > 0){
  244. RL_N_begin_delay_flag = 0;
  245. RL_N_end_delay_flag = 0;
  246. if(RL_N_ON_flag > 0){
  247. DB_Out4_H;
  248. RL_N_ON_flag = 0;
  249. AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr] = AC3PPDU_RL_N_time.LT_state | 0x00000001;
  250. }else if(RL_N_OFF_flag > 0)
  251. {
  252. DB_Out4_L;
  253. RL_N_OFF_flag = 0;
  254. AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr] = AC3PPDU_RL_N_time.LT_state | 0xfffffffe;
  255. }else{
  256. }
  257. //lock
  258. BUFF_Data;
  259. LOCK_Data;
  260. }
  261. for(i = 0;i < Output_ChN_default;i++)
  262. {
  263. RL_now_state[i] = AC3PPDU_RL_time[i + CH1_out].LT_state & 0x01;
  264. if(RL_last_state[i] != RL_now_state[i])
  265. {
  266. if(RL_now_state[i] > 0)//开启
  267. {
  268. RL_ON_flag[i] = 1;
  269. RL_OFF_flag[i] = 0;
  270. if((AC3PPDU_RL_time[i + CH1_out].LT_state & 0x40) > 0)//有延时
  271. {
  272. RL_begin_delay_flag[i] = 1;
  273. RL_end_delay_flag[i] = 0;
  274. RL_delay_Limit[i] = AC3PPDU_RL_time[i + CH1_out].RL_ontime * 1000;//秒转成毫秒
  275. }
  276. else//无延时
  277. {
  278. RL_begin_delay_flag[i] = 0;
  279. RL_end_delay_flag[i] = 1;
  280. RL_delay_Limit[i] = 0;
  281. }
  282. }
  283. else//断开
  284. {
  285. RL_OFF_flag[i] = 1;
  286. RL_ON_flag[i] = 0;
  287. if((AC3PPDU_RL_time[i + CH1_out].LT_state & 0x80) > 0)//有延时
  288. {
  289. RL_begin_delay_flag[i] = 1;
  290. RL_end_delay_flag[i] = 0;
  291. RL_delay_Limit[i] = AC3PPDU_RL_time[i + CH1_out].RL_offtime * 1000;//秒转成毫秒
  292. }
  293. else//无延时
  294. {
  295. RL_begin_delay_flag[i] = 0;
  296. RL_end_delay_flag[i] = 1;
  297. }
  298. }
  299. RL_last_state[i] = RL_now_state[i];
  300. }
  301. else
  302. {
  303. // if(OutUnit_control_flag[i] > 0)
  304. // {
  305. // OutUnit_control_flag[i] = 0;
  306. // }
  307. }
  308. ///////
  309. if(RL_end_delay_flag[i] > 0)
  310. {
  311. RL_begin_delay_flag[i] = 0;
  312. RL_end_delay_flag[i] = 0;
  313. if(RL_ON_flag[i] > 0)
  314. {
  315. //Relayx_Onoff_state(i,RELAY_ON);
  316. // setting relay status
  317. switch (i)
  318. {
  319. case 0:
  320. DB_Out1_H;
  321. break;
  322. case 1:
  323. DB_Out2_H;
  324. break;
  325. case 2:
  326. DB_Out3_H;
  327. break;
  328. }
  329. RL_ON_flag[i] = 0;
  330. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] = AC3PPDU_RL_time[i + CH1_out].LT_state | 0x00000001;
  331. AC3PPDU_Modbus_Reg[Mb_Dbuff_OUTCH1_ST_Addr + (i % 3)] = AC3PPDU_RL_time[i + CH1_out].LT_state | 0x00000001;
  332. }
  333. else if(RL_OFF_flag[i] > 0)
  334. {
  335. //Relayx_Onoff_state(i,RELAY_OFF);
  336. RL_OFF_flag[i] = 0;
  337. switch (i)
  338. {
  339. case 0:
  340. DB_Out1_L;
  341. break;
  342. case 1:
  343. DB_Out2_L;
  344. break;
  345. case 2:
  346. DB_Out3_L;
  347. break;
  348. }
  349. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] = AC3PPDU_RL_time[i + CH1_out].LT_state & 0xfffffffe;
  350. AC3PPDU_Modbus_Reg[Mb_Dbuff_OUTCH1_ST_Addr + (i % 3)] = AC3PPDU_RL_time[i + CH1_out].LT_state & 0xfffffffe;
  351. }
  352. //Write_74hc573(LK_Relay_D,Relay_state);
  353. BUFF_Data;
  354. LOCK_Data;
  355. }
  356. }
  357. RL_Allon_flag = false;
  358. RL_Alloff_flag = false;
  359. }
  360. }
  361. }
  362. static void LimiT_enable_check(uint8_t ch_x,uint32_t Lt_v)
  363. {
  364. uint16_t temp0 = 0;
  365. temp0 = Lt_v >> 1;
  366. if(ch_x > 3)
  367. {
  368. return;
  369. }
  370. //通道最大电压
  371. if((temp0 & AC3PPDU_Vmax_LT_enable) == AC3PPDU_Vmax_LT_enable)
  372. {
  373. AC3PPDU_Vmax_LTen_flag[ch_x] = 1;
  374. }
  375. else
  376. {
  377. AC3PPDU_Vmax_LTen_flag[ch_x] = 0;
  378. }
  379. //最小电压
  380. if((temp0 & AC3PPDU_Vmin_LT_enable) == AC3PPDU_Vmin_LT_enable)
  381. {
  382. AC3PPDU_Vmin_LTen_flag[ch_x] = 1;
  383. }
  384. else
  385. {
  386. AC3PPDU_Vmin_LTen_flag[ch_x] = 0;
  387. }
  388. //最大电流
  389. if((temp0 & AC3PPDU_Imax_LT_enable) == AC3PPDU_Imax_LT_enable)
  390. {
  391. AC3PPDU_Imax_LTen_flag[ch_x] = 1;
  392. }
  393. else
  394. {
  395. AC3PPDU_Imax_LTen_flag[ch_x] = 0;
  396. }
  397. //最大功率
  398. if((temp0 & AC3PPDU_Wmax_LT_enable) == AC3PPDU_Wmax_LT_enable)
  399. {
  400. AC3PPDU_Wmax_LTen_flag[ch_x] = 1;
  401. }
  402. else
  403. {
  404. AC3PPDU_Wmax_LTen_flag[ch_x] = 0;
  405. }
  406. //最大电量
  407. if((temp0 & AC3PPDU_kWhmax_LT_enable) == AC3PPDU_kWhmax_LT_enable)
  408. {
  409. AC3PPDU_kWhmax_LTen_flag[ch_x] = 1;
  410. }
  411. else
  412. {
  413. AC3PPDU_kWhmax_LTen_flag[ch_x] = 0;
  414. }
  415. }
  416. static void check_3_phse()
  417. {
  418. uint8_t Phase_3_Close_flag=0;
  419. if(3 == Phase_N){
  420. for(int i = 0 ; i < Output_ChN_default; i += 3 )
  421. {
  422. Phase_3_Close_flag = 0;
  423. for(int j = 1;j <= 3;j++)
  424. {
  425. if(RL_Func_statu[j+i] == 1)
  426. {
  427. Phase_3_Close_flag = 1;
  428. break;
  429. }
  430. }
  431. if(Phase_3_Close_flag)
  432. {
  433. for(int j = 1;j <= 3;j++)
  434. {
  435. RL_Func_statu[j+i] = 1;
  436. }
  437. }
  438. Phase_3_Close_flag = 0;
  439. }
  440. }
  441. }
  442. static void RL_Over_Func()
  443. {
  444. check_3_phse();
  445. if(RL_All_Func)
  446. {
  447. DB_Out1_L;
  448. DB_Out2_L;
  449. DB_Out3_L;
  450. for(int i = 0; i < Output_ChN_default;i++)
  451. {
  452. AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xfffffffe;
  453. RL_now_state[i] = AC3PPDU_RL_time[i + CH1_out].LT_state & 0x01;
  454. if(RL_now_state[i] != RL_last_state[i])
  455. {
  456. RL_last_state[i] = RL_now_state[i];
  457. }
  458. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] = AC3PPDU_RL_time[i + CH1_out].LT_state;
  459. AC3PPDU_Modbus_Reg[Mb_Dbuff_OUTCH1_ST_Addr + (i % 3)] = AC3PPDU_RL_time[i + CH1_out].LT_state;
  460. }
  461. RL_All_Func = 0;
  462. BUFF_Data;
  463. LOCK_Data;
  464. return;
  465. }
  466. for(int i = 0; i < Output_ChN_default;i++)
  467. {
  468. if(RL_Func_statu[i+1])
  469. {
  470. switch(i)
  471. {
  472. case 0:
  473. DB_Out1_L;
  474. break;
  475. case 1:
  476. DB_Out2_L;
  477. break;
  478. case 2:
  479. DB_Out3_L;
  480. break;
  481. case 3:
  482. case 4:
  483. case 5:
  484. case 6:
  485. case 7:
  486. case 8:
  487. default:
  488. break;
  489. }
  490. AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xfffffffe;
  491. RL_now_state[i] = AC3PPDU_RL_time[i + CH1_out].LT_state & 0x01;
  492. if(RL_now_state[i] != RL_last_state[i])
  493. {
  494. RL_last_state[i] = RL_now_state[i];
  495. }
  496. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] = AC3PPDU_RL_time[i + CH1_out].LT_state;
  497. AC3PPDU_Modbus_Reg[Mb_Dbuff_OUTCH1_ST_Addr + (i % 3)] = AC3PPDU_RL_time[i + CH1_out].LT_state;
  498. RL_Func_statu[i+1] = 0;
  499. }
  500. }
  501. BUFF_Data;
  502. LOCK_Data;
  503. }
  504. static void key_io_control()
  505. {
  506. bool rst = false;
  507. bool test = false;
  508. //
  509. rst = get_rst();
  510. test = get_test();
  511. if(get_detection())
  512. {
  513. AC3PPDU_Modbus_Reg[Mb_Dbuff_Detection] = 0x1;
  514. }else
  515. {
  516. AC3PPDU_Modbus_Reg[Mb_Dbuff_Detection] = 0x0;
  517. //close
  518. DB_Out1_L;
  519. DB_Out2_L;
  520. DB_Out3_L;
  521. for(uint8_t i = 0; i < Output_ChN_default;i++)
  522. {
  523. AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xfffffffe;
  524. RL_now_state[i] = AC3PPDU_RL_time[i + CH1_out].LT_state & 0x01;
  525. uint8_t stat = AC3PPDU_RL_time[i + CH1_out].LT_state;
  526. if(RL_now_state[i] != RL_last_state[i])
  527. {
  528. RL_last_state[i] = RL_now_state[i];
  529. }
  530. // save value to eeprom
  531. AT24CxxWriteOneByte(ERom_CH1LT_ST_Addr+i,stat);
  532. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] = AC3PPDU_RL_time[i + CH1_out].LT_state;
  533. AC3PPDU_Modbus_Reg[Mb_Dbuff_OUTCH1_ST_Addr + (i % 3)] = AC3PPDU_RL_time[i + CH1_out].LT_state;
  534. }
  535. }
  536. if(rst != test)
  537. {
  538. if(rst)
  539. {
  540. DB_Out1_L;
  541. DB_Out2_L;
  542. DB_Out3_L;
  543. for(uint8_t i = 0; i < Output_ChN_default;i++)
  544. {
  545. AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xfffffffe;
  546. RL_now_state[i] = AC3PPDU_RL_time[i + CH1_out].LT_state & 0x01;
  547. uint8_t stat = AC3PPDU_RL_time[i + CH1_out].LT_state;
  548. if(RL_now_state[i] != RL_last_state[i])
  549. {
  550. RL_last_state[i] = RL_now_state[i];
  551. }
  552. // save value to eeprom
  553. AT24CxxWriteOneByte(ERom_CH1LT_ST_Addr+i,stat);
  554. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] = AC3PPDU_RL_time[i + CH1_out].LT_state;
  555. AC3PPDU_Modbus_Reg[Mb_Dbuff_OUTCH1_ST_Addr + (i % 3)] = AC3PPDU_RL_time[i + CH1_out].LT_state;
  556. }
  557. }else
  558. {
  559. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Detection] == 0x1)
  560. {
  561. DB_Out1_H;
  562. DB_Out2_H;
  563. DB_Out3_H;
  564. for(uint8_t i = 0; i < Output_ChN_default;i++)
  565. {
  566. AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state | 0x00000001;
  567. RL_now_state[i] = AC3PPDU_RL_time[i + CH1_out].LT_state & 0x01;
  568. if(RL_now_state[i] != RL_last_state[i])
  569. {
  570. RL_last_state[i] = RL_now_state[i];
  571. }
  572. // save value to eeprom
  573. uint8_t stat = AC3PPDU_RL_time[i + CH1_out].LT_state;
  574. AT24CxxWriteOneByte(ERom_CH1LT_ST_Addr+i,stat);
  575. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] = AC3PPDU_RL_time[i + CH1_out].LT_state;
  576. AC3PPDU_Modbus_Reg[Mb_Dbuff_OUTCH1_ST_Addr + (i % 3)] = AC3PPDU_RL_time[i + CH1_out].LT_state | 0x00000001;
  577. }
  578. }
  579. }
  580. }
  581. BUFF_Data;
  582. LOCK_Data;
  583. }
  584. int main(void)
  585. {
  586. app_init(&meta_data);
  587. InitSysTick();
  588. InitLED();
  589. InitKey();
  590. InitTimer();
  591. InitRelay();
  592. Init_74hc573();
  593. InitAT24Cxx();
  594. InitUART1(9600);
  595. InitCH448F();
  596. AC3PPDU_SlaveAddress = ReadKeyValue();
  597. eMBInit(MB_RTU, AC3PPDU_SlaveAddress, 0, 115200, MB_PAR_NONE);
  598. eMBEnable();
  599. key_io_init(NULL);
  600. for(int i = 1; i <= AC3PPDU_active_chn;i++)
  601. {
  602. hlw8110_init(i);
  603. }
  604. ReadEeprom();
  605. AC3PPDU_active_chn = Output_ChN_default;
  606. strcpy(infomation.date,__DATE__);
  607. strcat(infomation.date," ");
  608. strcat(infomation.date,__TIME__);
  609. strcpy(infomation.ver,VERSION);
  610. int size = sizeof(infomation);
  611. Devid_IDChalNum = AC3PPDU_Device_ID;
  612. Devid_IDChalNum = Devid_IDChalNum << 8;
  613. Devid_IDChalNum += Output_ChN_default;
  614. AC3PPDU_Modbus_Reg[Mb_Dbuff_DevAddr] = Devid_IDChalNum;
  615. infomation.channels = Output_ChN_default;
  616. flash_get_infomation(&infomation);
  617. AC3PPDU_RL_time[CH_in].LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_LT_ST_Addr];
  618. AC3PPDU_RL_time[CH_in].FT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr];
  619. LimiT_enable_check(CH_in,AC3PPDU_RL_time[CH_in].LT_state);
  620. Enable_74hc573_Output;
  621. // Fault_state_Last = Fault_state_Reg;
  622. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] = AC3PPDU_APlack_Fault + AC3PPDU_BPlack_Fault;
  623. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] += AC3PPDU_CPlack_Fault;
  624. for(int i = 0;i < Output_ChN_default;i++)
  625. {
  626. RL_last_state[i] = 0;
  627. AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i];
  628. AC3PPDU_RL_time[i + CH1_out].RL_ontime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Ton1_Addr + i];
  629. AC3PPDU_RL_time[i + CH1_out].RL_offtime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Toff1_Addr + i];
  630. LimiT_enable_check((i + CH1_out),AC3PPDU_RL_time[i + CH1_out].LT_state);
  631. }
  632. RL_N_last_state = 0;
  633. AC3PPDU_RL_N_time.LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr]; // add by liyi
  634. AC3PPDU_RL_N_time.RL_offtime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_ToffN_Addr]; // add by liyi
  635. AC3PPDU_RL_N_time.RL_ontime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_TonN_Addr]; // add by liyi
  636. Fwdgt_Init();
  637. while(1)
  638. {
  639. CHK_JLINK();
  640. eMBPoll();
  641. Fwdgt_reload();
  642. if(flash_flag == 1){
  643. LEDFlicker2();
  644. flash_flag = 0;
  645. for(int j = 0 ; j < Hlw8110_CS;j++)
  646. read_Hlw8110(j,0);
  647. normal_running_time+=2;
  648. }
  649. if(write_kwh2Eeprom_flag) // 120 second recode
  650. {
  651. write_kwh2Eeprom_flag = 0;
  652. for(int i = 0; i < Output_ChN_default ;i++)
  653. {
  654. int temp = i << 2;
  655. Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+0] = AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr+i] >> 24;
  656. Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+1] = AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr+i] >> 16;
  657. Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+2] = AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr+i] >> 8;
  658. Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+3] = AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr+i];
  659. }
  660. AT24CxxWrite(ERom_TotalWh1_Addr,(Eeprom_Rbuf + ERom_TotalWh1_Addr),4*Output_ChN_default);
  661. }
  662. AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] = AC3PPDU_Output[CH1_out].AC_V;
  663. AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] = AC3PPDU_Output[CH2_out].AC_V;
  664. AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] = AC3PPDU_Output[CH3_out].AC_V;
  665. AC3PPDU_Modbus_Reg[Mb_Dbuff_IAP_Addr] = AC3PPDU_Output[CH1_out].AC_I;
  666. AC3PPDU_Modbus_Reg[Mb_Dbuff_IBP_Addr] = AC3PPDU_Output[CH2_out].AC_I;
  667. AC3PPDU_Modbus_Reg[Mb_Dbuff_ICP_Addr] = AC3PPDU_Output[CH3_out].AC_I;
  668. AC3PPDU_Modbus_Reg[Mb_Dbuff_WAP_Addr] = AC3PPDU_Output[CH1_out].AC_P;
  669. AC3PPDU_Modbus_Reg[Mb_Dbuff_WBP_Addr] = AC3PPDU_Output[CH2_out].AC_P;
  670. AC3PPDU_Modbus_Reg[Mb_Dbuff_WCP_Addr] = AC3PPDU_Output[CH3_out].AC_P;
  671. AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr] = hlw8110_base[CH1_out] + (hlw8110_store[CH1_out]*1000);
  672. AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhBP_Addr] = hlw8110_base[CH2_out] + (hlw8110_store[CH2_out]*1000);
  673. AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhCP_Addr] = hlw8110_base[CH3_out] + (hlw8110_store[CH3_out]*1000);
  674. for(int i = 0;i < (Output_ChN_default + 1);i++)
  675. {
  676. Fault_state_process(i);
  677. }
  678. RL_Over_Func();
  679. MODbus_CMD_New();
  680. }
  681. }
  682. static void MODbus_CMD_New(void)
  683. {
  684. if(Modbus_Wr_buff[Wr_eeprom_cnt][0] > 0)
  685. {
  686. uint8_t i = 0;
  687. uint32_t temp_addr;
  688. uint32_t base_addr = Modbus_Wr_buff[Wr_eeprom_cnt][1];
  689. uint32_t data = Modbus_Wr_buff[Wr_eeprom_cnt][2];
  690. uint32_t value = 0;
  691. switch(base_addr)
  692. {
  693. case Mb_Dbuff_ViLit_max_Addr ... Mb_Dbuff_kWhiLit_max_Addr: //input votage max votage min current power coustermer add by liyi
  694. {
  695. temp_addr = base_addr - Mb_Dbuff_ViLit_max_Addr;
  696. temp_addr = temp_addr << 2;
  697. temp_addr += ERom_ViLit_max_Addr;
  698. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  699. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  700. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  701. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  702. AC3PPDU_Modbus_Reg[base_addr] = data;
  703. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  704. }
  705. break;
  706. case Mb_Dbuff_VLit1_max_Addr ... Mb_Dbuff_VLit9_max_Addr: //output voltage max threod for 1,2,3,4,5,6,7,8,9 channels
  707. {
  708. temp_addr = base_addr - Mb_Dbuff_VLit1_max_Addr;
  709. value = temp_addr;
  710. temp_addr = temp_addr << 2;
  711. temp_addr += ERom_VLit1_max_Addr;
  712. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  713. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  714. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  715. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  716. AC3PPDU_Modbus_Reg[base_addr] = data;
  717. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  718. {
  719. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Vmax_Threshould_Disable);
  720. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  721. }
  722. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  723. }
  724. break;
  725. case Mb_Dbuff_VLit1_min_Addr ... Mb_Dbuff_VLit9_min_Addr: //output voltage min thred for 1,2,3,4,5,6,7,8,9 channels
  726. {
  727. temp_addr = base_addr - Mb_Dbuff_VLit1_min_Addr;
  728. value = temp_addr;
  729. temp_addr = temp_addr << 2;
  730. temp_addr += ERom_VLit1_min_Addr;
  731. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  732. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  733. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  734. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  735. AC3PPDU_Modbus_Reg[base_addr] = data;
  736. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  737. {
  738. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Vmin_Threshould_Disable);
  739. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  740. }
  741. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  742. }
  743. break;
  744. case Mb_Dbuff_ILit1_max_Addr ... Mb_Dbuff_ILit9_max_Addr: // output current max throud for 1,2,3,4,5,6,7,8,9 channels
  745. {
  746. temp_addr = base_addr - Mb_Dbuff_ILit1_max_Addr;
  747. value = temp_addr;
  748. temp_addr = temp_addr << 2;
  749. temp_addr += ERom_ILit1_max_Addr;
  750. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  751. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  752. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  753. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  754. AC3PPDU_Modbus_Reg[base_addr] = data;
  755. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  756. {
  757. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Imax_Threshould_Disable);
  758. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  759. }
  760. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  761. }
  762. break;
  763. case Mb_Dbuff_WLit1_max_Addr ... Mb_Dbuff_WLit9_max_Addr: //output power max .....
  764. {
  765. temp_addr = base_addr - Mb_Dbuff_WLit1_max_Addr;
  766. value = temp_addr;
  767. temp_addr = temp_addr << 2;
  768. temp_addr += ERom_WLit1_max_Addr;
  769. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  770. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  771. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  772. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  773. AC3PPDU_Modbus_Reg[base_addr] = data;
  774. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  775. {
  776. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Wmax_Threshould_Disable);
  777. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  778. }
  779. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  780. }
  781. break;
  782. case Mb_Dbuff_kWhLit1_max_Addr ... Mb_Dbuff_kWhLit9_max_Addr: //output customers max .....
  783. {
  784. temp_addr = base_addr - Mb_Dbuff_kWhLit1_max_Addr;
  785. value = temp_addr;
  786. temp_addr = temp_addr << 2;
  787. temp_addr += ERom_kWhLit1_max_Addr;
  788. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  789. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  790. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  791. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  792. AC3PPDU_Modbus_Reg[base_addr] = data;
  793. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  794. {
  795. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Kwhmax_Threshould_Disable);
  796. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  797. }
  798. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  799. }
  800. break;
  801. case Mb_Dbuff_RL_Allon_Addr: //relay all on
  802. {
  803. RL_Allon_flag = true;
  804. for(i = 0;i < Output_ChN_default;i++)
  805. {
  806. temp_addr = i << 1;
  807. Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
  808. AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
  809. }
  810. AT24CxxWrite(ERom_CH1LT_ST_Addr,(Eeprom_Rbuf + ERom_CH1LT_ST_Addr),(2*Output_ChN_default));
  811. Eeprom_Rbuf[ERom_CHNLT_ST_Addr] = Eeprom_Rbuf[ERom_CHNLT_ST_Addr] | 0x41;
  812. AC3PPDU_RL_N_time.LT_state = Eeprom_Rbuf[ERom_CHNLT_ST_Addr];
  813. AT24CxxWrite(ERom_CHNLT_ST_Addr,(Eeprom_Rbuf + ERom_CHNLT_ST_Addr),2);
  814. }
  815. break;
  816. case Mb_Dbuff_RL_Alloff_Addr: //relay all off
  817. {
  818. RL_Alloff_flag = true;
  819. for(i = 0;i < Output_ChN_default;i++)
  820. {
  821. temp_addr = i << 1;
  822. Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
  823. Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
  824. AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
  825. }
  826. AT24CxxWrite(ERom_CH1LT_ST_Addr,(Eeprom_Rbuf + ERom_CH1LT_ST_Addr),(2*Output_ChN_default));
  827. Eeprom_Rbuf[ERom_CHNLT_ST_Addr] = Eeprom_Rbuf[ERom_CHNLT_ST_Addr] | 0x80;
  828. Eeprom_Rbuf[ERom_CHNLT_ST_Addr] = Eeprom_Rbuf[ERom_CHNLT_ST_Addr] & 0xfe;
  829. AC3PPDU_RL_N_time.LT_state = Eeprom_Rbuf[ERom_CHNLT_ST_Addr];
  830. AT24CxxWrite(ERom_CHNLT_ST_Addr,(Eeprom_Rbuf + ERom_CHNLT_ST_Addr),2);
  831. }
  832. break;
  833. case Mb_Dbuff_LT_ST_Addr: //set input status
  834. {
  835. AC3PPDU_RL_time[CH_in].LT_state = data;
  836. Eeprom_Rbuf[ERom_LT_ST_Addr] = data;
  837. AC3PPDU_Modbus_Reg[base_addr] = data;
  838. AT24CxxWriteOneByte(ERom_LT_ST_Addr,Eeprom_Rbuf[ERom_LT_ST_Addr]);
  839. LimiT_enable_check(CH_in,AC3PPDU_RL_time[CH_in].LT_state);
  840. }
  841. break;
  842. case Mb_Dbuff_CH1LT_ST_Addr ... Mb_Dbuff_CHNLT_ST_Addr: //set output relay statues
  843. {
  844. temp_addr = base_addr - Mb_Dbuff_CH1LT_ST_Addr;
  845. // if(temp_addr == 9) { //Ch N
  846. // AC3PPDU_RL_N_time.LT_state = data;
  847. // }else{
  848. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  849. {
  850. data &= (Shield_Vmax_Threshould_Disable);
  851. }
  852. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  853. {
  854. data &= (Shield_Vmin_Threshould_Disable);
  855. }
  856. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  857. {
  858. data &= (Shield_Imax_Threshould_Disable);
  859. }
  860. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  861. {
  862. data &= (Shield_Wmax_Threshould_Disable);
  863. }
  864. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  865. {
  866. data &= (Shield_Kwhmax_Threshould_Disable);
  867. }
  868. AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
  869. LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
  870. // }
  871. temp_addr = temp_addr << 1;
  872. temp_addr += ERom_CH1LT_ST_Addr;
  873. Eeprom_Rbuf[temp_addr] = data;
  874. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  875. }
  876. break;
  877. case Mb_Dbuff_OUTCH1_ST_Addr ... Mb_Dbuff_OUTCH3_ST_Addr: //set output channel relay's status
  878. {
  879. temp_addr = base_addr - Mb_Dbuff_OUTCH1_ST_Addr;
  880. //OutUnit_control_flag[temp_addr] = 1;
  881. temp_addr *= 3;
  882. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  883. {
  884. data &= (Shield_Vmax_Threshould_Disable);
  885. }
  886. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  887. {
  888. data &= (Shield_Vmin_Threshould_Disable);
  889. }
  890. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  891. {
  892. data &= (Shield_Imax_Threshould_Disable);
  893. }
  894. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  895. {
  896. data &= (Shield_Wmax_Threshould_Disable);
  897. }
  898. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  899. {
  900. data &= (Shield_Kwhmax_Threshould_Disable);
  901. }
  902. AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
  903. AC3PPDU_RL_time[temp_addr + CH2_out].LT_state = data;
  904. AC3PPDU_RL_time[temp_addr + CH3_out].LT_state = data;
  905. LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
  906. LimiT_enable_check((temp_addr + CH2_out),AC3PPDU_RL_time[temp_addr + CH2_out].LT_state);
  907. LimiT_enable_check((temp_addr + CH3_out),AC3PPDU_RL_time[temp_addr + CH3_out].LT_state);
  908. temp_addr = temp_addr << 1;
  909. Eeprom_Rbuf[temp_addr + ERom_CH1LT_ST_Addr] = data;
  910. Eeprom_Rbuf[temp_addr + ERom_CH2LT_ST_Addr] = data;
  911. Eeprom_Rbuf[temp_addr + ERom_CH3LT_ST_Addr] = data;
  912. AT24CxxWriteOneByte(temp_addr + ERom_CH1LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH1LT_ST_Addr]);
  913. AT24CxxWriteOneByte(temp_addr + ERom_CH2LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH2LT_ST_Addr]);
  914. AT24CxxWriteOneByte(temp_addr + ERom_CH3LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH3LT_ST_Addr]);
  915. }
  916. break;
  917. case Mb_Dbuff_RL_Ton1_Addr ... Mb_Dbuff_RL_TonN_Addr: //set on status delay for 1,2,3,4,5,6,7,8,9,N channels
  918. {
  919. temp_addr = base_addr - Mb_Dbuff_RL_Ton1_Addr;
  920. if(temp_addr == 9){ //Ch N add by liyi
  921. AC3PPDU_RL_N_time.RL_ontime = data;
  922. }else
  923. {
  924. AC3PPDU_RL_time[temp_addr + CH1_out].RL_ontime = data;
  925. }
  926. AC3PPDU_RL_N_time.RL_ontime = data;
  927. temp_addr += ERom_RL_Ton1_Addr;
  928. Eeprom_Rbuf[temp_addr] = data;
  929. Eeprom_Rbuf[ERom_RL_TonN_Addr] = data;
  930. AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
  931. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_TonN_Addr] = Eeprom_Rbuf[ERom_RL_TonN_Addr];
  932. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  933. AT24CxxWriteOneByte(ERom_RL_TonN_Addr,Eeprom_Rbuf[ERom_RL_TonN_Addr]);
  934. }
  935. break;
  936. case Mb_Dbuff_RL_Toff1_Addr ... Mb_Dbuff_RL_ToffN_Addr: //set off status delay for 1,2,3,4,5,6,7,8,9,N channels
  937. {
  938. temp_addr = base_addr - Mb_Dbuff_RL_Toff1_Addr;
  939. if(temp_addr == 9){
  940. AC3PPDU_RL_N_time.RL_offtime = data;
  941. }else {
  942. AC3PPDU_RL_time[temp_addr + CH1_out].RL_offtime = data;
  943. }
  944. AC3PPDU_RL_N_time.RL_offtime = data;
  945. temp_addr += ERom_RL_Toff1_Addr;
  946. Eeprom_Rbuf[temp_addr] = data;
  947. Eeprom_Rbuf[ERom_RL_ToffN_Addr] = data;
  948. AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
  949. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_ToffN_Addr] = Eeprom_Rbuf[ERom_RL_ToffN_Addr];
  950. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  951. AT24CxxWriteOneByte(ERom_RL_ToffN_Addr,Eeprom_Rbuf[ERom_RL_ToffN_Addr]);
  952. }
  953. break;
  954. case Mb_Dbuff_RL_Over_Ch1_Func ... Mb_Dbuff_RL_Over_Ch9_Func: //threod over limit operation
  955. {
  956. temp_addr = base_addr - Mb_Dbuff_RL_Over_Ch1_Func;
  957. temp_addr += ERom_RL_Over_Ch1_Addr;
  958. Eeprom_Rbuf[temp_addr] = data;
  959. AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
  960. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  961. }
  962. break;
  963. case Mb_Dbuff_Clear_Chn1_Consumer ... Mb_Dbuff_Clear_Chn9_Consumer:
  964. {
  965. if(data)
  966. {
  967. temp_addr = base_addr - Mb_Dbuff_Clear_Chn1_Consumer;
  968. hlw8110_base[temp_addr+CH1_out] = 0;
  969. hlw8110_store[temp_addr+CH1_out] = 0.0;
  970. }
  971. }
  972. case Mb_Dbuff_Clear_Chnall_Consumer:
  973. {
  974. if(data){
  975. for(i = 0; i < Output_ChN_default;i++)
  976. {
  977. hlw8110_base[i+CH1_out] = 0;
  978. hlw8110_store[i+CH1_out] = 0.0;
  979. }
  980. }
  981. }
  982. break;
  983. case Mb_Dbuff_All_ViLit_Max ... Mb_Dbuff_All_kWhiLit_Max:
  984. {
  985. temp_addr = base_addr - Mb_Dbuff_All_ViLit_Max;
  986. temp_addr = temp_addr << 2;
  987. temp_addr += ERom_VILit_All_max_Addr;
  988. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  989. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  990. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  991. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  992. AC3PPDU_Modbus_Reg[base_addr] = data;
  993. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  994. switch (base_addr - Mb_Dbuff_All_ViLit_Max)
  995. {
  996. case 0:
  997. {
  998. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  999. {
  1000. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Vmax_Threshould_Disable);
  1001. }else
  1002. {
  1003. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_Vmax_Threshould_enable);
  1004. }
  1005. }
  1006. break;
  1007. case 1:
  1008. {
  1009. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  1010. {
  1011. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Vmin_Threshould_Disable);
  1012. }else
  1013. {
  1014. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_Vmin_Threshould_enable);
  1015. }
  1016. }
  1017. break;
  1018. case 2:
  1019. {
  1020. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  1021. {
  1022. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Imax_Threshould_Disable);
  1023. }else
  1024. {
  1025. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_Imax_Threshould_enable);
  1026. }
  1027. }
  1028. break;
  1029. case 3:
  1030. {
  1031. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  1032. {
  1033. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Wmax_Threshould_Disable);
  1034. }else
  1035. {
  1036. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_Wmax_Threshould_enable);
  1037. }
  1038. }
  1039. break;
  1040. case 4:
  1041. {
  1042. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  1043. {
  1044. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Kwhmax_Threshould_Disable);
  1045. }else
  1046. {
  1047. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_kWhmax_Threshould_enable);
  1048. }
  1049. }
  1050. break;
  1051. }
  1052. }
  1053. break;
  1054. case Mb_Dbuff_All_OverFunc:
  1055. {
  1056. temp_addr = base_addr - Mb_Dbuff_All_OverFunc;
  1057. temp_addr += Mb_Dbuff_All_OverFunc;
  1058. Eeprom_Rbuf[temp_addr] = data;
  1059. AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
  1060. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  1061. }
  1062. break;
  1063. case Mb_Dbuff_break_Addr:
  1064. {
  1065. break_2_boot_upgreade();
  1066. }
  1067. break;
  1068. default:
  1069. break;
  1070. }
  1071. Modbus_Wr_buff[Wr_eeprom_cnt][0] = 0;
  1072. //Wr_eeprom_begin_flag = true;
  1073. }
  1074. Wr_eeprom_cnt++;
  1075. if(Wr_eeprom_cnt >= Mb_Wcmd_Width)
  1076. {
  1077. Wr_eeprom_cnt = 0;
  1078. }
  1079. }
  1080. //static void MODbus_CMD_New(void)
  1081. //{
  1082. // if(Modbus_Wr_buff[Wr_eeprom_cnt][0] > 0)
  1083. // {
  1084. // uint8_t i = 0;
  1085. // uint32_t temp_addr;
  1086. // uint32_t base_addr = Modbus_Wr_buff[Wr_eeprom_cnt][1];
  1087. // uint32_t data = Modbus_Wr_buff[Wr_eeprom_cnt][2];
  1088. // uint32_t value = 0;
  1089. //
  1090. // switch(base_addr)
  1091. // {
  1092. // case Mb_Dbuff_RL_Allon_Addr:
  1093. // {
  1094. // DB_Out1_H;
  1095. // DB_Out2_H;
  1096. // DB_Out3_H;
  1097. // BUFF_Data;
  1098. // LOCK_Data;
  1099. // }
  1100. // break;
  1101. // case Mb_Dbuff_RL_Alloff_Addr:
  1102. // {
  1103. // DB_Out1_L;
  1104. // DB_Out2_L;
  1105. // DB_Out3_L;
  1106. // BUFF_Data;
  1107. // LOCK_Data;
  1108. // }
  1109. // break;
  1110. // }
  1111. // Modbus_Wr_buff[Wr_eeprom_cnt][0] = 0;
  1112. // }
  1113. // Wr_eeprom_cnt++;
  1114. // if(Wr_eeprom_cnt >= Mb_Wcmd_Width)
  1115. // {
  1116. // Wr_eeprom_cnt = 0;
  1117. // }
  1118. //}
  1119. static void Fault_state_process(uint8_t ch_x)
  1120. {
  1121. uint16_t i = 0;
  1122. if(ch_x != CH_in)
  1123. i = (ch_x -1)<< 3;
  1124. if(ch_x == CH_in)
  1125. {
  1126. uint32_t sort_buff[3] = {0};
  1127. uint32_t Vmax = 0;
  1128. uint32_t Vmin = 0;
  1129. sort_buff[0] = AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr];
  1130. sort_buff[1] = AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr];
  1131. sort_buff[2] = AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr];
  1132. Vmax = (sort_buff[0] >= sort_buff[1]) ? sort_buff[0] :sort_buff[1];
  1133. Vmax = (Vmax >= sort_buff[2]) ? Vmax : sort_buff[2];
  1134. Vmin = (sort_buff[0] <= sort_buff[1]) ? sort_buff[0] :sort_buff[1];
  1135. Vmin = (Vmin <= sort_buff[2]) ? Vmin : sort_buff[2];
  1136. if((Vmin < AC3PPDU_Lack_Voltage) && (Vmax != 0) && (Vmax > (AC3PPDU_Lack_Voltage*2)))
  1137. {
  1138. uint32_t v_mid = AC3PPDU_Lack_Voltage *2;
  1139. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] < v_mid)
  1140. {
  1141. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackA_Addr] = 1;
  1142. }
  1143. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] < v_mid)
  1144. {
  1145. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackB_Addr] = 1;
  1146. }
  1147. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] < v_mid)
  1148. {
  1149. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackC_Addr] =1;
  1150. }
  1151. }else
  1152. {
  1153. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackA_Addr] = 0;
  1154. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackB_Addr] = 0;
  1155. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackC_Addr] = 0;
  1156. }
  1157. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_Vmax_Threshould_enable) > 0)
  1158. {
  1159. if(AC_BASE[0] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_ViLit_Max])
  1160. {
  1161. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Vmax_Fault;
  1162. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmin_NFault;
  1163. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_V_Max_Func_enable)
  1164. {
  1165. RL_All_Func = 1;
  1166. }
  1167. }else if(AC_BASE[0] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_ViLit_Min])
  1168. {
  1169. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmax_NFault;
  1170. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmin_NFault;
  1171. }else
  1172. {
  1173. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmax_NFault;
  1174. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Vmin_Fault;
  1175. }
  1176. }
  1177. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_Vmin_Threshould_enable) > 0)
  1178. {
  1179. if(AC_BASE[0] < AC3PPDU_Modbus_Reg[Mb_Dbuff_All_ViLit_Min])
  1180. {
  1181. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Vmin_Fault;
  1182. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_V_Min_Func_enable)
  1183. {
  1184. RL_All_Func = 1;
  1185. }
  1186. }
  1187. else//小于最小
  1188. {
  1189. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmin_NFault;
  1190. }
  1191. }
  1192. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_Imax_Threshould_enable) > 0)
  1193. {
  1194. if(AC_BASE[1] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_IiLit_Max])
  1195. {
  1196. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Imax_Fault;
  1197. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_I_Max_Func_enable)
  1198. {
  1199. RL_All_Func = 1;
  1200. }
  1201. }
  1202. else
  1203. {
  1204. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Imax_NFault;
  1205. }
  1206. }
  1207. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_Wmax_Threshould_enable) > 0)
  1208. {
  1209. if(AC_BASE[2] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_WiLit_Max])
  1210. {
  1211. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Wmax_Fault;
  1212. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_P_Max_Func_enable)
  1213. {
  1214. RL_All_Func = 1;
  1215. }
  1216. }
  1217. else
  1218. {
  1219. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Wmax_NFault;
  1220. }
  1221. }
  1222. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_kWhmax_Threshould_enable) > 0)
  1223. {
  1224. if(AC_BASE[3] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_kWhiLit_Max])
  1225. {
  1226. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_kWhmax_Fault;
  1227. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_C_Max_Func_enable)
  1228. {
  1229. RL_All_Func = 1;
  1230. }
  1231. }
  1232. else
  1233. {
  1234. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_kWhmax_NFault;
  1235. }
  1236. }
  1237. return;
  1238. }
  1239. ////电压最大、最小、缺相阈值使能,进行判断
  1240. if(AC3PPDU_Vmax_LTen_flag[ch_x] > 0)
  1241. {
  1242. if(ch_x > CH_in)//输出通道
  1243. {
  1244. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + ch_x-1])//大于最大
  1245. {
  1246. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Vmax_Fault;
  1247. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmin_NFault;
  1248. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func+ch_x-1] & (AC3PPDU_Over_V_Max_Func_enable)) //is or not open func
  1249. {
  1250. RL_Func_statu[ch_x] = 1;
  1251. }
  1252. }
  1253. else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + ch_x-1])//大于最小,小于最大,正常
  1254. {
  1255. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmax_NFault;
  1256. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmin_NFault;
  1257. }
  1258. else//小于最小
  1259. {
  1260. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmax_NFault;
  1261. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Vmin_Fault;
  1262. }
  1263. }
  1264. else//输入通道
  1265. {
  1266. //A相
  1267. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_max_Addr])//超限
  1268. {
  1269. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AVmax_Fault;
  1270. }
  1271. else
  1272. {
  1273. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmax_NFault;
  1274. }
  1275. //B相
  1276. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_max_Addr])//超限
  1277. {
  1278. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BVmax_Fault;
  1279. }
  1280. else
  1281. {
  1282. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmax_NFault;
  1283. }
  1284. //C相
  1285. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_max_Addr])//超限
  1286. {
  1287. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CVmax_Fault;
  1288. }
  1289. else
  1290. {
  1291. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmax_NFault;
  1292. }
  1293. }
  1294. }
  1295. else
  1296. {
  1297. if(ch_x > CH_in)
  1298. {
  1299. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmax_NFault;
  1300. }
  1301. else
  1302. {
  1303. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmax_NFault;
  1304. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmax_NFault;
  1305. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmax_NFault;
  1306. }
  1307. }
  1308. //最小电压
  1309. if(AC3PPDU_Vmin_LTen_flag[ch_x] > 0)
  1310. {
  1311. if(ch_x > CH_in)//输出通道
  1312. {
  1313. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + i] < AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + ch_x -1])//大于最大 revice by liyi max -> min
  1314. {
  1315. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Vmin_Fault;
  1316. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func + ch_x - 1] & (AC3PPDU_Over_V_Min_Func_enable)) //is or not open func add by liyi
  1317. {
  1318. RL_Func_statu[ch_x] = 1;
  1319. }
  1320. }
  1321. else//小于最小
  1322. {
  1323. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmin_NFault;
  1324. }
  1325. }
  1326. else//输入通道
  1327. {
  1328. //A相
  1329. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_min_Addr])//
  1330. {
  1331. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmin_NFault;
  1332. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_APlack_NFault;
  1333. }
  1334. else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] > 1000)
  1335. {
  1336. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AVmin_Fault;
  1337. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_APlack_NFault;
  1338. }
  1339. else
  1340. {
  1341. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmin_NFault;
  1342. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_APlack_Fault;
  1343. }
  1344. //B相
  1345. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_min_Addr])//
  1346. {
  1347. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmin_NFault;
  1348. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BPlack_NFault;
  1349. }
  1350. else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] > 1000)
  1351. {
  1352. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BVmin_Fault;
  1353. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BPlack_NFault;
  1354. }
  1355. else
  1356. {
  1357. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmin_NFault;
  1358. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BPlack_Fault;
  1359. }
  1360. //C相
  1361. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_min_Addr])//超限
  1362. {
  1363. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmin_NFault;
  1364. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CPlack_NFault;
  1365. }
  1366. else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] > 1000)
  1367. {
  1368. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CVmin_Fault;
  1369. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CPlack_NFault;
  1370. }
  1371. else
  1372. {
  1373. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmin_NFault;
  1374. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CPlack_Fault;
  1375. }
  1376. }
  1377. }
  1378. else
  1379. {
  1380. if(ch_x > CH_in)
  1381. {
  1382. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmin_NFault;
  1383. }
  1384. else
  1385. {
  1386. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmin_NFault;
  1387. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmin_NFault;
  1388. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmin_NFault;
  1389. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] > 1000)
  1390. {
  1391. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_APlack_NFault;
  1392. }
  1393. else
  1394. {
  1395. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_APlack_Fault;
  1396. }
  1397. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] > 1000)
  1398. {
  1399. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BPlack_NFault;
  1400. }
  1401. else
  1402. {
  1403. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BPlack_Fault;
  1404. }
  1405. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] > 1000)
  1406. {
  1407. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CPlack_NFault;
  1408. }
  1409. else
  1410. {
  1411. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CPlack_Fault;
  1412. }
  1413. }
  1414. }
  1415. //电流最大
  1416. if(AC3PPDU_Imax_LTen_flag[ch_x] > 0)
  1417. {
  1418. if(ch_x > CH_in)//输出通道
  1419. {
  1420. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + 1 + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + ch_x -1])
  1421. {
  1422. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Imax_Fault;
  1423. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func + ch_x-1] & (AC3PPDU_Over_I_Max_Func_enable)) //is or not open func add by liyi
  1424. {
  1425. RL_Func_statu[ch_x] = 1;
  1426. }
  1427. }
  1428. else
  1429. {
  1430. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Imax_NFault;
  1431. }
  1432. }
  1433. else//输入通道
  1434. {
  1435. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_IAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_IiLit_max_Addr]))//超限
  1436. {
  1437. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AImax_Fault;
  1438. }
  1439. else
  1440. {
  1441. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AImax_NFault;
  1442. }
  1443. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_IBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_IiLit_max_Addr]))//超限
  1444. {
  1445. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BImax_Fault;
  1446. }
  1447. else
  1448. {
  1449. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BImax_NFault;
  1450. }
  1451. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ICP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_IiLit_max_Addr]))//超限
  1452. {
  1453. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CImax_Fault;
  1454. }
  1455. else
  1456. {
  1457. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CImax_NFault;
  1458. }
  1459. }
  1460. }
  1461. else
  1462. {
  1463. if(ch_x > CH_in)
  1464. {
  1465. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Imax_NFault;
  1466. }
  1467. else
  1468. {
  1469. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AImax_NFault;
  1470. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BImax_NFault;
  1471. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CImax_NFault;
  1472. }
  1473. }
  1474. //功率最大
  1475. if(AC3PPDU_Wmax_LTen_flag[ch_x] > 0)
  1476. {
  1477. if(ch_x > CH_in)//输出通道
  1478. {
  1479. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + 2 + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + ch_x -1])
  1480. {
  1481. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Wmax_Fault;
  1482. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func + ch_x-1] & (AC3PPDU_Over_P_Max_Func_enable)) //is or not open func add by liyi
  1483. {
  1484. RL_Func_statu[ch_x] = 1;
  1485. }
  1486. }
  1487. else
  1488. {
  1489. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Wmax_NFault;
  1490. }
  1491. }
  1492. else//输入通道
  1493. {
  1494. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1495. {
  1496. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AWmax_Fault;
  1497. }
  1498. else
  1499. {
  1500. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AWmax_NFault;
  1501. }
  1502. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1503. {
  1504. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BWmax_Fault;
  1505. }
  1506. else
  1507. {
  1508. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BWmax_NFault;
  1509. }
  1510. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WCP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1511. {
  1512. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CWmax_Fault;
  1513. }
  1514. else
  1515. {
  1516. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CWmax_NFault;
  1517. }
  1518. }
  1519. }
  1520. else
  1521. {
  1522. if(ch_x > CH_in)
  1523. {
  1524. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Wmax_NFault;
  1525. }
  1526. else
  1527. {
  1528. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AWmax_NFault;
  1529. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BWmax_NFault;
  1530. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CWmax_NFault;
  1531. }
  1532. }
  1533. //电量最大
  1534. if(AC3PPDU_kWhmax_LTen_flag[ch_x] > 0)
  1535. {
  1536. if(ch_x > CH_in)//输出通道
  1537. {
  1538. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + 6 + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + ch_x-1])
  1539. {
  1540. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_kWhmax_Fault;
  1541. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func + ch_x-1] & (AC3PPDU_Over_C_Max_Func_enable)) //is or not open func add by liyi
  1542. {
  1543. RL_Func_statu[ch_x] = 1;
  1544. }
  1545. }
  1546. else
  1547. {
  1548. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_kWhmax_NFault;
  1549. }
  1550. }
  1551. else//输入通道
  1552. {
  1553. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1554. {
  1555. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AkWhmax_Fault;
  1556. }
  1557. else
  1558. {
  1559. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AkWhmax_NFault;
  1560. }
  1561. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1562. {
  1563. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BkWhmax_Fault;
  1564. }
  1565. else
  1566. {
  1567. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BkWhmax_NFault;
  1568. }
  1569. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhCP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1570. {
  1571. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CkWhmax_Fault;
  1572. }
  1573. else
  1574. {
  1575. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CkWhmax_NFault;
  1576. }
  1577. }
  1578. }
  1579. else
  1580. {
  1581. if(ch_x > CH_in)
  1582. {
  1583. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_kWhmax_NFault;
  1584. }
  1585. else
  1586. {
  1587. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AkWhmax_NFault;
  1588. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BkWhmax_NFault;
  1589. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CkWhmax_NFault;
  1590. }
  1591. }
  1592. }
  1593. #ifdef USE_FULL_ASSERT
  1594. void assert_failed(uint8_t* file, uint32_t line)
  1595. {
  1596. while (1);
  1597. }
  1598. #else
  1599. void __aeabi_assert(const char * x1, const char * x2, int x3)
  1600. {
  1601. (void)x3;
  1602. }
  1603. #endif