cascade.c 29 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155
  1. #include "cascade.h"
  2. #include "mb.h"
  3. #include "lock.h"
  4. #include "list.h"
  5. #include "modbus.h"
  6. #include <rtthread.h>
  7. #include <unistd.h>
  8. #include "pthread.h"
  9. #include "stdio.h"
  10. #include "string.h"
  11. #include "power.h"
  12. #include "paras.h"
  13. #include "thread.h"
  14. #define REGS(x) (((x)+(x)%2)/2)
  15. typedef void * handle_t;
  16. typedef struct {
  17. mb_inst_t *hinst;
  18. uint8_t mode;
  19. uint8_t type;
  20. rt_thread_t tid;
  21. uint8_t quit;
  22. }mb_handle_t;
  23. typedef struct {
  24. union {
  25. md_ac_dc_t ac_dc;
  26. md_3_ac_t ac_3;
  27. }data;
  28. }north_data_t;
  29. typedef struct cascade_saddr{
  30. uint8_t addr;
  31. uint16_t channels;
  32. power_ch_new_t ch[POWER_SLAVE_CH_MAX];
  33. }slave_info_t;
  34. typedef union{
  35. slave_info_t info;
  36. north_data_t north;
  37. }cascade_data_cache;
  38. typedef struct cascade_info{
  39. uint8_t switch_flag;
  40. uint8_t saddr;
  41. uint8_t read_addr;
  42. uint8_t md_type;
  43. uint32_t bund;
  44. uint8_t quit;
  45. lock_t lock;
  46. slave_t slaves[POWER_CASCADE_MAX+1];
  47. cmd_data_t cmd;
  48. cascade_data_cache *chache;
  49. mb_inst_t *tcp_hinst;
  50. mb_backend_param_t param;
  51. }cascade_handle_t;
  52. static int sendlen=0; //级联读取offset
  53. static cascade_handle_t slave_info = {0}; //自维护全局变量
  54. static mb_cascade_fun_t func = {0}; //匹配mdbus 回调函数
  55. const mb_cb_table_t mb_table = {
  56. .read_disc = mb_port_read_disc, //读离散量输入
  57. .read_coil = mb_port_read_coil, //读线圈
  58. .write_coil = mb_port_write_coil, //写线圈
  59. .read_input = mb_port_read_input, //读输入寄存器
  60. .read_hold = mb_port_read_hold, //读保持寄存器
  61. .write_hold = mb_port_write_hold, //写保持寄存器
  62. };
  63. static int mb_write_read(cascade_handle_t *cas, int addr, data_t *wd, data_t *rd);
  64. static int master_query(cascade_handle_t *cas);
  65. static void slave_func(uint16_t reg,void *r_w_data,uint32_t lenth);
  66. static int slave_get_info(cascade_handle_t *cas);
  67. static int master_cmd(cascade_handle_t *cas,uint8_t cur_dev_addr ,cmd_data_t *cmd);
  68. static void slave_rm(uint8_t addr);
  69. static void memswap(uint8_t *buf, int len);
  70. static void * my_memcpy_byte(void *dst, const void *src, int n);
  71. static uint8_t master_scan(cascade_handle_t *cas);
  72. static int _mb_write(cascade_handle_t *cas, int addr, data_t *d);
  73. static int _mb_read(cascade_handle_t *cas, int addr, data_t *d);
  74. static void* off_on_thread(void *arg); //主机控制从机开关线程
  75. static void memswap(uint8_t *buf, int len)
  76. {
  77. int i;
  78. uint8_t tmp;
  79. for(i=0; i<len; i+=2) {
  80. tmp = buf[i];
  81. buf[i] = buf[i+1];
  82. buf[i+1] = tmp;
  83. }
  84. }
  85. static void slave_rm(uint8_t addr)
  86. {
  87. if(addr > 0 && addr < POWER_SLAVE_CH_MAX)
  88. {
  89. slave_info.slaves[addr].addr = 0;
  90. slave_info.slaves[addr].err = 0;
  91. }
  92. }
  93. static uint8_t master_scan(cascade_handle_t *cas)
  94. {
  95. #if SUPPORT_CASCADE_QMODBUS
  96. static uint8_t slave_addr = 1;
  97. if(slave_addr > POWER_CASCADE_MAX)
  98. {
  99. slave_addr = 1;
  100. }
  101. if(cas->slaves[slave_addr].addr == 0)
  102. {
  103. //scan
  104. uint16_t value = 0;
  105. lock_on(cas->lock);
  106. int r = mb_read(MB_ID_CASCADE,slave_addr,CASCADE_REG_SCAN,&value,1,300);
  107. lock_off(cas->lock);
  108. if(r > 0)
  109. {
  110. LOGD("scan slave addr %d !!!\n",slave_addr);
  111. cas->slaves[slave_addr].addr = slave_addr;
  112. cas->slaves[slave_addr].err = 0;
  113. }
  114. }
  115. slave_addr++;
  116. #endif
  117. }
  118. static int slave_get_info(cascade_handle_t *cas)
  119. {
  120. #if SUPPORT_CASCADE_QMODBUS
  121. slave_info_t *info = &cas->chache->info;
  122. power_handle_new_t *p_handle = power_get_all();
  123. info->channels = p_handle->chs;
  124. for(int i=0; i < info->channels;i++)
  125. {
  126. info->ch[i] = p_handle->pch[i];
  127. }
  128. LOGD("slave will send %d channels to master!!!!\n",info->channels);
  129. #endif
  130. return 0;
  131. }
  132. static void *my_memcpy_byte(void *dst, const void *src, int n)
  133. {
  134. if (dst == NULL || src == NULL || n <= 0)
  135. return NULL;
  136. char * pdst = (char *)dst;
  137. char * psrc = (char *)src;
  138. if (pdst > psrc && pdst < psrc + n)
  139. {
  140. pdst = pdst + n - 1;
  141. psrc = psrc + n - 1;
  142. while (n--)
  143. *pdst-- = *psrc--;
  144. }
  145. else
  146. {
  147. while (n--)
  148. *pdst++ = *psrc++;
  149. }
  150. return dst;
  151. }
  152. static void slave_func(uint16_t reg,void *r_w_data,uint32_t lenth)
  153. {
  154. #if SUPPORT_CASCADE_QMODBUS
  155. cmd_data_t *cmd=NULL;
  156. pthread_t id = 0;
  157. power_handle_new_t *p_handle = power_get_all();
  158. switch (reg)
  159. {
  160. case CASCADE_REG_SCAN:
  161. break;
  162. case CASCADE_REG_WRITE:
  163. {
  164. cmd = (cmd_data_t*)(r_w_data);
  165. if(cmd->cmd>=CASCADE_CMD_GET_INFO) {
  166. //slave_info.cmd = *cmd;
  167. memcpy(&slave_info.cmd,r_w_data,sizeof(cmd_data_t));
  168. sendlen = slave_info.cmd.c_m.sendlen_offset;
  169. }
  170. //LOGD("____write_____ %d\n",lenth);
  171. // sendlen = 0;
  172. switch(cmd->cmd)
  173. {
  174. case CASCADE_CMD_OPEN:
  175. case CASCADE_CMD_CLOSE:
  176. {
  177. cmd_data_t *pcmd=malloc(sizeof(cmd_data_t));
  178. if(pcmd) {
  179. *pcmd = *cmd;
  180. pthread_create(&id,NULL,off_on_thread,pcmd);
  181. pthread_detach(id);
  182. }
  183. }
  184. break;
  185. case CASCADE_CMD_OPEN_NF:
  186. case CASCADE_CMD_CLOSE_NF:
  187. {
  188. }
  189. break;
  190. case CASCADE_CMD_SAVE:
  191. case CASCADE_CMD_SAVE3:
  192. {
  193. }
  194. break;
  195. case CASCADE_CMD_BREAKER_SAVE_ADD:
  196. {
  197. }
  198. break;
  199. case CASCADE_CMD_BREAKER_SAVE_UPDATE:
  200. {
  201. }
  202. break;
  203. case CASCADE_CMD_BREAKER_SAVE_DELETE:
  204. {
  205. }
  206. break;
  207. }
  208. }
  209. break;
  210. case CASCADE_REG_READ:
  211. {
  212. cmd = &slave_info.cmd;
  213. switch(cmd->cmd)
  214. {
  215. case CASCADE_CMD_GET_INFO:
  216. {
  217. uint8_t * base_addr = (uint8_t *)&p_handle->pch[0];
  218. //my_memcpy_byte(r_w_data,base_addr+sendlen,lenth*2);
  219. memcpy(r_w_data,base_addr+sendlen,lenth*2);
  220. memswap(r_w_data,lenth*2);
  221. LOGD("____read_____ readlen = %d,sendlen = %d power_ch_t size=%d\n",lenth,sendlen,sizeof(power_ch_t));
  222. }
  223. break;
  224. case CASCADE_CMD_QUERY_CH:
  225. {
  226. uint8_t * base_addr = (uint8_t *)&p_handle->pch[0];
  227. my_memcpy_byte(r_w_data,base_addr+sendlen,lenth*2);
  228. memswap(r_w_data,lenth*2);
  229. }
  230. break;
  231. case CASCADE_CMD_BREAKER_QUERY:
  232. break;
  233. case CASCADE_CMD_QUERY_VOL:break;
  234. case CASCADE_CMD_QUERY_CUR:break;
  235. case CASCADE_CMD_QUERY_PWR:break;
  236. case CASCADE_CMD_QUERY_PWRQ:break;
  237. case CASCADE_CMD_QUERY_HIS:break;
  238. case CASCADE_CMD_QUERY_TOTAL:break;
  239. case CASCADE_CMD_QUERY_TOTAL_PWR:break;
  240. case CASCADE_CMD_BREAKER_GET_INFO:break;
  241. }
  242. //sendlen += lenth*2;
  243. }
  244. break;
  245. default:
  246. {
  247. }
  248. break;
  249. }
  250. #endif
  251. }
  252. static int _mb_write(cascade_handle_t *cas, int addr, data_t *d)
  253. {
  254. int i = 0,r=0,timeout=0;
  255. #if SUPPORT_CASCADE_QMODBUS
  256. int wl,xlen,wlen=0,oncelen=250;
  257. uint8_t retry = 5;
  258. uint8_t buff[MB_BUF_SIZE+100];
  259. if(d->dlen<=0) {
  260. return -1;
  261. }
  262. lock_on(cas->lock);
  263. for(;i < retry;i++)
  264. {
  265. while(1)
  266. {
  267. if(wlen+oncelen>d->dlen) {
  268. xlen = d->dlen-wlen;
  269. } else
  270. {
  271. xlen = oncelen;
  272. }
  273. xlen += xlen%2;
  274. memcpy(buff, d->data+wlen, xlen);
  275. //交换数据
  276. memswap(buff,xlen%2+xlen);
  277. wl = mb_write(MB_ID_CASCADE, addr, CASCADE_REG_WRITE, (uint16_t*)buff, xlen/2);
  278. if(wl<=0) {
  279. LOGE("___ _mb_write failed, addr: %d, reg: %d, cnt: %d, %s, retry: %d errno = %d \n", addr, CASCADE_REG_WRITE, xlen/2,"write failed",i+1,wl);
  280. if(addr >0 && addr < POWER_SLAVE_CH_MAX)
  281. {
  282. slave_info.slaves[addr].err ++;
  283. if(slave_info.slaves[addr].err > 5)
  284. {
  285. slave_rm(addr);
  286. }
  287. }
  288. r = -1;
  289. break;
  290. }else
  291. {
  292. slave_info.slaves[addr].err = 0;
  293. r = 0;
  294. }
  295. if(wlen+wl*2>=d->dlen) {
  296. break;
  297. }else {
  298. xlen = wl*2;
  299. }
  300. wlen += xlen;
  301. }
  302. if(r == 0)
  303. break;
  304. }
  305. lock_off(cas->lock);
  306. return r;
  307. #endif
  308. }
  309. static int _mb_read(cascade_handle_t *cas, int addr, data_t *d)
  310. {
  311. int i=0,r=0,finish=0,timeout=0;
  312. #if SUPPORT_CASCADE_QMODBUS
  313. int rl,xlen,rlen=0,oncelen=250;
  314. uint8_t retry = 5;
  315. uint16_t buff[MB_BUF_SIZE];
  316. if(d->dlen<=0) {
  317. return -1;
  318. }
  319. lock_on(cas->lock);
  320. for(i =0;i < retry;i++)
  321. {
  322. while(1) {
  323. if(rlen+oncelen>d->dlen) {
  324. xlen = d->dlen-rlen;
  325. }else{
  326. xlen = oncelen;
  327. }
  328. xlen += xlen%2;
  329. rl = mb_read(MB_ID_CASCADE, addr, CASCADE_REG_READ, buff, xlen/2,100);
  330. if(rl<=0) {
  331. LOGE("___ _mb_read failed, %s, rlen: %d, retry: %d\n", "read error", rlen, i+1);
  332. if(addr >0 && addr < POWER_SLAVE_CH_MAX)
  333. {
  334. cas->slaves[addr].err ++;
  335. if(cas->slaves[addr].err > 5)
  336. {
  337. slave_rm(addr);
  338. }
  339. }
  340. r = -1; break;
  341. }else
  342. {
  343. cas->slaves[addr].err =0;
  344. }
  345. if(rlen+rl*2>=d->dlen) {
  346. xlen = d->dlen-rlen;
  347. finish = 1;
  348. }else
  349. {
  350. xlen = rl*2;
  351. }
  352. memcpy((char*)d->data+rlen, buff, xlen);
  353. rlen += xlen;
  354. if(finish) {
  355. r = 0;
  356. break;
  357. }
  358. }
  359. if(r==0)
  360. break;
  361. }
  362. lock_off(cas->lock);
  363. #endif
  364. return r;
  365. }
  366. static int mb_write_read(cascade_handle_t *cas, int addr, data_t *wd, data_t *rd)
  367. {
  368. int r =0;
  369. #if SUPPORT_CASCADE_QMODBUS
  370. r = _mb_write(cas, addr,wd);
  371. if(r==0) {
  372. r = _mb_read(cas, addr,rd);
  373. }
  374. #endif
  375. return r;
  376. }
  377. static int mb_write_read_n(cascade_handle_t *cas, int addr, data_t *wd, data_t *rd)
  378. {
  379. int i=0,r=0,finish=0,timeout=0;
  380. #if SUPPORT_CASCADE_QMODBUS
  381. int rl,xlen,rlen=0,oncelen=250;
  382. uint16_t buff[MB_BUF_SIZE];
  383. while(1) {
  384. //set sendlen = rlen;
  385. cas->cmd.c_m.sendlen_offset = rlen;
  386. wd->dlen = sizeof(cmd_data_t);
  387. wd->data = (uint8_t*)&(cas->cmd);
  388. r = _mb_write(cas, addr,wd);
  389. //set need transport len
  390. if(rlen+oncelen>rd->dlen) {
  391. xlen = rd->dlen-rlen;
  392. }else{
  393. xlen = oncelen;
  394. }
  395. xlen += xlen%2;
  396. lock_on(cas->lock);
  397. while(1)
  398. {
  399. rl = mb_read(MB_ID_CASCADE, addr, CASCADE_REG_READ, buff, xlen/2,200);
  400. if(rl<=0) {
  401. if(addr >0 && addr < POWER_SLAVE_CH_MAX) {
  402. cas->slaves[addr].err ++;
  403. LOGE("___ _mb_read failed, %s, rlen: %d, retry: %d ernno=%d\n", "read error", rlen, cas->slaves[addr].err,rl);
  404. if(cas->slaves[addr].err > 5) {
  405. slave_rm(addr);
  406. lock_off(cas->lock);
  407. goto fail;
  408. }
  409. }else {
  410. lock_off(cas->lock);
  411. goto fail;
  412. }
  413. }else {
  414. cas->slaves[addr].err =0;
  415. break;
  416. }
  417. }
  418. lock_off(cas->lock);
  419. if(rlen+rl*2>=rd->dlen) {
  420. xlen = rd->dlen-rlen;
  421. finish = 1;
  422. }else {
  423. xlen = rl*2;
  424. }
  425. memcpy((char*)rd->data+rlen, buff, xlen);
  426. rlen += xlen;
  427. if(finish) {
  428. r = 0;
  429. break;
  430. }
  431. }
  432. #endif
  433. fail:
  434. return r;
  435. }
  436. static void* off_on_thread(void *arg)
  437. {
  438. #if SUPPORT_CASCADE_QMODBUS
  439. cascade_handle_t *cas=&slave_info;
  440. cmd_data_t *pcmd=(cmd_data_t*)arg;
  441. if(pcmd->cmd==CASCADE_CMD_OPEN) {
  442. // LOGD("____ slave CASCADE_CMD_OPEN\n");
  443. }
  444. else {
  445. // LOGD("____ slave CASCADE_CMD_CLOSE\n");
  446. }
  447. int flag=((pcmd->cmd==CASCADE_CMD_OPEN)?1:0);
  448. if(pcmd->chId == 0xff) {
  449. // all
  450. }else
  451. {
  452. //one
  453. }
  454. if(pcmd->cmd==CASCADE_CMD_OPEN) {
  455. // sprintf(temp,"$开启$|$所有$|$通道$");
  456. }
  457. else {
  458. // sprintf(temp,"$关闭$|$所有$|$通道$");
  459. }
  460. //data base
  461. free(pcmd);
  462. pthread_exit(NULL);
  463. #endif
  464. }
  465. static int master_cmd(cascade_handle_t *cas,uint8_t cur_dev_addr ,cmd_data_t *cmd)
  466. {
  467. int i,r;
  468. #if SUPPORT_CASCADE_QMODBUS
  469. data_t rdata,wdata;
  470. if(cur_dev_addr==0) {
  471. return -1;
  472. }
  473. switch(cmd->cmd) {
  474. case CASCADE_CMD_OPEN:
  475. case CASCADE_CMD_CLOSE:
  476. case CASCADE_CMD_SAVE:
  477. case CASCADE_CMD_SAVE3:
  478. case CASCADE_CMD_OPEN_NF:
  479. case CASCADE_CMD_CLOSE_NF:
  480. {
  481. LOGD("____ master CMD: %d\n", cmd->cmd);
  482. wdata.dlen = sizeof(cmd_data_t);
  483. wdata.data = (uint8_t*)cmd;
  484. r = _mb_write(cas, cur_dev_addr, &wdata);
  485. }
  486. break;
  487. case CASCADE_CMD_GET_INFO:
  488. {
  489. wdata.dlen = sizeof(cmd_data_t);
  490. wdata.data = (uint8_t*)cmd;
  491. // rdata.dlen = sizeof(slave_info_t)-sizeof(power_ch_t)*POWER_SLAVE_CH_MAX;
  492. // rdata.data = (uint8_t*)cas->info;
  493. uint16_t value = 0;
  494. r = mb_read(MB_ID_CASCADE,cur_dev_addr,4000,&value,1,100);//获取通道数
  495. //r = mb_write_read(cas, cur_dev_addr, &wdata, &rdata);
  496. LOGD("r = %d value=%d\n",r,value);
  497. if(r == 1)
  498. {
  499. uint8_t chanels = value & 0xff;
  500. if(chanels == 0 || chanels > 100)
  501. {
  502. cas->chache->info.channels = 0;
  503. LOGD("get slave channels %d!!!\n",chanels);
  504. }else
  505. {
  506. if(chanels >= POWER_SLAVE_CH_MAX)
  507. chanels = POWER_SLAVE_CH_MAX;
  508. cas->chache->info.channels = chanels;
  509. //rdata.dlen = sizeof(slave_info_t) -sizeof(power_ch_t)*(POWER_SLAVE_CH_MAX - cas->info.channels);
  510. rdata.dlen = sizeof(power_ch_t)*cas->chache->info.channels;
  511. rdata.data = (uint8_t*)&(cas->chache->info.ch);
  512. r = mb_write_read_n(cas, cur_dev_addr, &wdata, &rdata);
  513. if(r==0) {
  514. }else
  515. {
  516. LOGE("_____ master CASCADE_CMD_GET_INFO read failed\n");
  517. }
  518. }
  519. }
  520. // if(r==0) {
  521. // rdata.dlen = sizeof(slave_info_t)-sizeof(power_ch_t)*(POWER_SLAVE_CH_MAX - cas->info.channels);
  522. // rdata.data = (uint8_t*)&cas->info;
  523. // r = mb_write_read(cas, cur_dev_addr, &wdata, &rdata);
  524. // if(r==0) {
  525. // }else
  526. // {
  527. // LOGE("_____ master CASCADE_CMD_GET_INFO read failed\n");
  528. // }
  529. // }
  530. // else {
  531. // LOGE("_____ master CASCADE_CMD_GET_INFO failed\n");
  532. // }
  533. }
  534. break;
  535. case CASCADE_CMD_BREAKER_GET_INFO:
  536. {
  537. }
  538. break;
  539. case CASCADE_CMD_BREAKER_SAVE_UPDATE:
  540. case CASCADE_CMD_BREAKER_SAVE_DELETE:
  541. case CASCADE_CMD_BREAKER_SAVE_ADD:
  542. {
  543. }
  544. break;
  545. default:
  546. cas->cmd = *cmd;
  547. r = 0;
  548. }
  549. #endif
  550. return r;
  551. }
  552. static void timer1_callback(void *parameter)
  553. {
  554. #if 0
  555. timer1_cnt++;
  556. rt_kprintf("timer1 callback execute %d times\n", timer1_cnt);
  557. /* 执行5次后,将自身周期修改为250ms */
  558. if (timer1_cnt == 5) {
  559. rt_kprintf("timer1 change period to 250ms.\n");
  560. rt_timer_control(timer1, RT_TIMER_CTRL_SET_TIME, (void *)250);
  561. }
  562. #endif
  563. }
  564. void cascade_tcp_thread(void *arg)
  565. {
  566. while(1) {
  567. mb_slave_fsm(slave_info.tcp_hinst);
  568. usleep(60000);
  569. }
  570. pthread_exit(NULL);
  571. }
  572. uint8_t cascade_init(void)
  573. {
  574. #if SUPPORT_CASCADE_QMODBUS
  575. paras_data_t* p_d = paras_get();
  576. memset(&slave_info,0,sizeof(slave_info));
  577. slave_info.quit = 1;
  578. slave_info.lock = lock_init();
  579. slave_info.md_type = p_d->cas.mode;
  580. slave_info.chache = (cascade_data_cache *) malloc(sizeof(cascade_data_cache));
  581. if(slave_info.chache == NULL)
  582. {
  583. lock_deinit(slave_info.lock);
  584. return -1;
  585. }
  586. //slave_info.cascade_timer = rt_timer_create("cascade_timer",timer1_callback,RT_NULL,10,RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_HARD_TIMER);
  587. LOGD("__casecde__malloc size if cascade %d\n",sizeof(cascade_data_cache));
  588. if(p_d->cas.mode == MB_MODE_SLAVE)
  589. {
  590. mb_set_addr(MB_ID_CASCADE,p_d->cas.addr);
  591. mb_set_cb(MB_ID_CASCADE, &mb_table);
  592. func.slave_func = slave_func;
  593. mb_set_cascade_cb(MB_ID_CASCADE,&func);
  594. memset(&slave_info.chache->north,0,sizeof(north_data_t));
  595. //rt_timer_start(slave_info.cascade_timer);
  596. }else if(p_d->cas.mode == MB_MODE_MASTER)
  597. {
  598. memset(&slave_info.chache->info,0,sizeof(slave_info_t));
  599. }else
  600. {
  601. LOGE("cascede mode type is err ____ %d!!!\n",p_d->cas.mode);
  602. free(slave_info.chache);
  603. slave_info.chache = 0;
  604. return -1;
  605. }
  606. slave_info.quit = 0;
  607. slave_info.read_addr = 1;
  608. LOGD("scan thread!!!\n");
  609. thread_start(THREAD_ID_CAS_SCAN,cascade_scan_thread,NULL);
  610. sleep(1);
  611. LOGD("cascade thread!!!\n");
  612. thread_start(THREAD_ID_CAS_TH,cascade_thread,NULL);
  613. //tcp modbus
  614. LOGD("modbus tcp thread!!!\n");
  615. //mb_slave_poll(MB_ID_TCP);
  616. //thread_start(THREAD_ID_CAS_TCP,cascade_tcp_thread,NULL);
  617. // strcpy(slave_info.param.tcp.host,"0.0.0.0");
  618. // slave_info.param.tcp.port = 502;
  619. // if(slave_info.tcp_hinst != NULL)
  620. // {
  621. // mb_disconn(slave_info.tcp_hinst);
  622. // slave_info.tcp_hinst = NULL;
  623. // }
  624. // slave_info.tcp_hinst = mb_create(MB_BACKEND_TYPE_TCP, &slave_info.param);
  625. // if(slave_info.tcp_hinst == NULL)
  626. // {
  627. // LOG_E("modbus tcp error!!!\n");
  628. // return -1;
  629. // }
  630. // mb_set_slave(slave_info.tcp_hinst,p_d->cas.addr);
  631. // mb_set_cb_table(slave_info.tcp_hinst,&mb_table);
  632. // mb_connect(slave_info.tcp_hinst);
  633. // LOGD("modbus tcp sucess!!!\n");
  634. // //mb_slave_fsm(pinf->hinst);
  635. // thread_start(THREAD_ID_CAS_TCP,cascade_tcp_thread,NULL);
  636. #endif
  637. return 0;
  638. }
  639. void cascade_reset_new(uint8_t mode,uint8_t addr,uint32_t baund)
  640. {
  641. #if SUPPORT_CASCADE_QMODBUS
  642. slave_info.switch_flag = 1;
  643. paras_data_t* p_d = paras_get();
  644. if(baund != p_d->cas.baud)
  645. {
  646. mb_deinit_n(MB_ID_CASCADE);
  647. mb_para_t m_para = {0};
  648. m_para.type = MB_TYPE_RTU;
  649. m_para.para.rtu.baudrate = baund;
  650. m_para.para.rtu.dev = CASCADE_PORT;
  651. m_para.para.rtu.parity = 0;
  652. m_para.para.rtu.pin = -1;
  653. m_para.para.rtu.lvl = 0;
  654. mb_init_n(MB_ID_CASCADE,&m_para);
  655. }
  656. if(mode != slave_info.md_type)
  657. {
  658. if(mode == MB_MODE_MASTER)
  659. {
  660. slave_info.md_type = MB_MODE_MASTER;
  661. memset(&slave_info.chache->info,0,sizeof(slave_info_t));
  662. //rt_timer_stop(slave_info.cascade_timer);
  663. }else
  664. {
  665. slave_info.md_type = MB_MODE_SLAVE;
  666. mb_set_addr(MB_ID_CASCADE,addr);
  667. mb_set_cb(MB_ID_CASCADE, &mb_table);
  668. func.slave_func = slave_func;
  669. mb_set_cascade_cb(MB_ID_CASCADE,&func);
  670. memset(&slave_info.chache->north,0,sizeof(north_data_t));
  671. //rt_timer_start(slave_info.cascade_timer);
  672. }
  673. }else
  674. {
  675. if(mode == MB_MODE_SLAVE)
  676. {
  677. if(addr != p_d->cas.addr)
  678. {
  679. mb_set_addr(MB_ID_CASCADE,addr);
  680. }
  681. }
  682. }
  683. p_d->cas.addr = addr;
  684. p_d->cas.baud = baund;
  685. p_d->cas.mode = mode;
  686. paras_save();
  687. slave_info.switch_flag = 0;
  688. #endif
  689. }
  690. void cascade_reset(uint8_t mode,uint8_t addr)
  691. {
  692. #if SUPPORT_CASCADE_QMODBUS
  693. slave_info.switch_flag = 1;
  694. paras_data_t* p_d = paras_get();
  695. if((p_d->cas.mode == MB_MODE_MASTER) && (slave_info.md_type != MB_MODE_MASTER))
  696. {
  697. slave_info.md_type = MB_MODE_MASTER;
  698. memset(&slave_info.chache->info,0,sizeof(slave_info_t));
  699. }else if((p_d->cas.mode == MB_MODE_SLAVE) && (slave_info.md_type != MB_MODE_SLAVE))
  700. {
  701. slave_info.md_type = MB_MODE_SLAVE;
  702. mb_set_addr(MB_ID_CASCADE,p_d->cas.addr);
  703. mb_set_cb(MB_ID_CASCADE, &mb_table);
  704. func.slave_func = slave_func;
  705. mb_set_cascade_cb(MB_ID_CASCADE,&func);
  706. memset(&slave_info.chache->north,0,sizeof(north_data_t));
  707. }else if(p_d->cas.mode == MB_MODE_SLAVE)
  708. {
  709. mb_set_addr(MB_ID_CASCADE,p_d->cas.addr);
  710. }else
  711. {
  712. return ;
  713. }
  714. paras_save();
  715. slave_info.switch_flag = 0;
  716. #endif
  717. }
  718. void cascade_scan_thread(void *arg)
  719. {
  720. #if SUPPORT_CASCADE_QMODBUS
  721. while(slave_info.quit == 0)
  722. {
  723. if(slave_info.switch_flag)
  724. {
  725. sleep(1);
  726. continue;
  727. }
  728. if(slave_info.md_type == MB_MODE_MASTER)
  729. {
  730. master_scan(&slave_info);
  731. sleep(1);
  732. }else //做从机//拷贝数据到北向
  733. {
  734. paras_data_t* p_data = paras_get();
  735. power_handle_new_t *all = power_get_all();
  736. if(p_data->prod.type == PDU_AC_I1O1 || p_data->prod.type == PDU_DC_I1O1)
  737. {
  738. int channels = all->chs;
  739. slave_info.chache->north.data.ac_dc.dev_cnt = (p_data->prod.type << 8 | channels);
  740. int cnt = all->chs > POWER_SLAVE_CH_MAX ? POWER_SLAVE_CH_MAX : channels;
  741. //电量信息
  742. for(int i = 0; i < cnt;i++)
  743. {
  744. slave_info.chache->north.data.ac_dc.power[i].voltage = all->pch[i].power[0].voltage *1000;
  745. slave_info.chache->north.data.ac_dc.power[i].current = all->pch[i].power[0].current *1000;
  746. slave_info.chache->north.data.ac_dc.power[i].power = all->pch[i].power[0].power *1000;
  747. slave_info.chache->north.data.ac_dc.power[i].consumer = all->pch[i].power[0].consump *1000;
  748. slave_info.chache->north.data.ac_dc.power[i].factor = all->pch[i].power[0].factor *1000;
  749. slave_info.chache->north.data.ac_dc.power[i].freq = all->pch[i].power[0].freq *1000;
  750. }
  751. //总信息
  752. //slave_info.chache->north.data.ac_dc.power_all. = all.ttl.total;
  753. slave_info.chache->north.data.ac_dc.power_all.all_consumer = all->total.all.consump *1000;
  754. slave_info.chache->north.data.ac_dc.power_all.all_current = all->total.all.current *1000;
  755. slave_info.chache->north.data.ac_dc.power_all.all_power = all->total.all.power *1000;
  756. slave_info.chache->north.data.ac_dc.power_all.all_voltage = all->total.all.voltage *1000;
  757. //温湿度
  758. slave_info.chache->north.data.ac_dc.temp = 0; //后续加上传感器数据
  759. slave_info.chache->north.data.ac_dc.humity = 0;
  760. for(int i = 0; i < cnt;i++)
  761. slave_info.chache->north.data.ac_dc.switch_stu[i] = 0;
  762. for(int i = 0; i < cnt;i++)
  763. {
  764. slave_info.chache->north.data.ac_dc.delay_open[i] = all->pch[i].info.open_delay;
  765. }
  766. for(int i = 0; i < cnt;i++)
  767. {
  768. slave_info.chache->north.data.ac_dc.delay_close[i] = all->pch[i].info.close_delay;
  769. }
  770. }else
  771. {
  772. int channels = all->chs > 0 ? all->chs: 0;
  773. slave_info.chache->north.data.ac_3.dev_cnt = (p_data->prod.type << 8 | channels);
  774. for(int i = A_P; i <= C_P;i++)
  775. {
  776. slave_info.chache->north.data.ac_3.ac_3_all_pw[i].consumer = all->total.all_l[i].consump *1000;
  777. slave_info.chache->north.data.ac_3.ac_3_all_pw[i].current = all->total.all_l[i].current *1000;
  778. slave_info.chache->north.data.ac_3.ac_3_all_pw[i].power = all->total.all_l[i].power *1000;
  779. slave_info.chache->north.data.ac_3.ac_3_all_pw[i].voltage = all->total.all_l[i].voltage *1000;
  780. }
  781. int cnt = all->chs > POWER_SLAVE_CH_MAX ? POWER_SLAVE_CH_MAX : channels;
  782. for(int i = 0; i < cnt;i++)
  783. {
  784. //总体信息
  785. }
  786. for(int i = 0; i < cnt;i++)
  787. {
  788. for(int j = A_P; j <= C_P;j++)
  789. {
  790. slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_consumer = all->pch[i].power[j].consump * 1000;
  791. slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_current = all->pch[i].power[j].current * 1000;
  792. slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_power = all->pch[i].power[j].power * 1000;
  793. slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_voltage = all->pch[i].power[j].voltage * 1000;
  794. slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_status = all->pch[i].info.status;
  795. }
  796. }
  797. for(int i = 0; i < cnt;i++)
  798. {
  799. slave_info.chache->north.data.ac_3.delay_open[i] = all->pch[i].info.open_delay;
  800. }
  801. for(int i = 0; i < cnt;i++)
  802. {
  803. slave_info.chache->north.data.ac_3.delay_close[i] = all->pch[i].info.close_delay;
  804. }
  805. }
  806. //LOGD("cpy data to north user\n");
  807. //slave_get_info(&slave_info);
  808. }
  809. sleep(1);
  810. }
  811. #endif
  812. }
  813. #if 0
  814. void cascade_tcp_thread(void *arg)
  815. {
  816. while(slave_info.quit==0) {
  817. mb_slave_poll(MB_ID_TCP);
  818. usleep(20000);
  819. }
  820. pthread_exit(NULL);
  821. }
  822. #endif
  823. void cascade_thread(void *arg)
  824. {
  825. #if SUPPORT_CASCADE_QMODBUS
  826. LOGD("__ cascade %s\n", (slave_info.md_type==MB_MODE_MASTER)?"master":"slave");
  827. while(slave_info.quit==0) {
  828. if(slave_info.switch_flag)
  829. {
  830. sleep(1);
  831. continue;
  832. }
  833. if(slave_info.md_type==MB_MODE_MASTER) { //主模
  834. cmd_data_t cmd;
  835. cmd.cmd = CASCADE_CMD_GET_INFO;
  836. cmd.obj = OBJ_OVERALL;
  837. slave_info.cmd = cmd;
  838. master_cmd(&slave_info,slave_info.read_addr,&cmd);
  839. sleep(1);
  840. }
  841. else { //从模式,等待主设备发起数据请求
  842. mb_slave_poll(MB_ID_CASCADE);
  843. usleep(20000);
  844. }
  845. }
  846. pthread_exit(NULL);
  847. #endif
  848. }
  849. int cascade_request(cmd_data_t *cmd)
  850. {
  851. master_cmd(&slave_info,1,cmd);
  852. return 0;
  853. }
  854. int mb_port_read_disc(u16 addr, u8 *pbit)//读离散量输入, 返回 : 0-成功, -2-地址错误
  855. {
  856. MB_ASSERT(pbit != NULL);
  857. return(-2);
  858. }
  859. int mb_port_read_coil(u16 addr, u8 *pbit)//读线圈, 返回 : 0-成功, -2-地址错误
  860. {
  861. MB_ASSERT(pbit != NULL);
  862. return(-2);
  863. }
  864. int mb_port_write_coil(u16 addr, u8 bit)//写线圈, 返回 : 0-成功, -2-地址错误, -4-设备故障
  865. {
  866. return(-2);
  867. }
  868. int mb_port_read_input(u16 addr, u16 *preg)//读输入寄存器, 返回 : 0-成功, -2-地址错误
  869. {
  870. MB_ASSERT(preg != NULL);
  871. return(-2);
  872. }
  873. int mb_port_read_hold(u16 addr, u16 *preg)//读保持寄存器, 返回 : 0-成功, -2-地址错误
  874. {
  875. MB_ASSERT(preg != NULL);
  876. uint16_t *data = NULL;
  877. if( AC_DC_DEV_CHN_REG <= addr && addr <= AC_DC_DRY_REG)
  878. {
  879. data = (uint16_t*)(&slave_info.chache->north.data.ac_dc);
  880. uint32_t offset = addr - AC_DC_DEV_CHN_REG;
  881. *preg = *(data+offset);
  882. return 0;
  883. }
  884. if(AC_3_DEV_CHN_REG <= addr && addr <= AC_3_DRY_REG)
  885. {
  886. data = (uint16_t*)(&slave_info.chache->north.data.ac_3);
  887. uint32_t offset = addr - AC_3_DEV_CHN_REG;
  888. *preg = *(data+offset);
  889. return 0;
  890. }
  891. return(-2);
  892. }
  893. int mb_port_write_hold(u16 addr, u16 reg)//写保持寄存器, 返回 : 0-成功, -2-地址错误, -3-值非法, -4-设备故障
  894. {
  895. power_handle_new_t *power = power_get_all();
  896. power_ch_new_t * pch = NULL;
  897. if(AC_DC_SET_DELAY_OPEN <= addr && addr <= AC_DC_ALL_SET_SWITCH_REG)
  898. {
  899. switch(addr)
  900. {
  901. case AC_DC_SET_DELAY_OPEN ... (AC_DC_SET_DELAY_CLOSE-1):
  902. {
  903. uint16_t channel = addr - AC_DC_SET_DELAY_OPEN;
  904. if(channel < power->chs)
  905. {
  906. pch = &power->pch[channel];
  907. uint16_t reg_close = power->pch[channel].info.close_delay;
  908. power->set_delay(pch->info.addr,pch->info.sch,reg,reg_close);
  909. }
  910. }
  911. break;
  912. case AC_DC_SET_DELAY_CLOSE ...(AC_DC_CHN_SET_SWITCH_STA_REG - 1):
  913. {
  914. uint16_t channel = addr - AC_DC_SET_DELAY_CLOSE;
  915. if(channel < power->chs)
  916. {
  917. pch = &power->pch[channel];
  918. uint16_t reg_open = power->pch[channel].info.open_delay;
  919. power->set_delay(power->pch[channel].info.addr,power->pch[channel].info.sch,reg_open,reg);
  920. }
  921. }
  922. break;
  923. case AC_DC_CHN_SET_SWITCH_STA_REG ... (AC_DC_ALL_SET_SWITCH_REG-1):
  924. {
  925. uint16_t channel = addr - AC_DC_CHN_SET_SWITCH_STA_REG;
  926. if(channel < power->chs)
  927. {
  928. pch = &power->pch[channel];
  929. power->set_status(pch->info.addr,pch->info.sch,reg);
  930. }
  931. }
  932. break;
  933. case AC_DC_ALL_SET_SWITCH_REG:
  934. {
  935. power->set_all_status(reg);
  936. }
  937. break;
  938. }
  939. return 0;
  940. }
  941. if(AC_3_SET_DELAY_OPEN <= addr && addr <= AC_3_ALL_SET_SWITCH_REG )
  942. {
  943. switch(addr)
  944. {
  945. case AC_3_SET_DELAY_OPEN ... (AC_3_SET_DELAY_CLOSE-1):
  946. {
  947. uint16_t channel = addr - AC_DC_SET_DELAY_OPEN;
  948. if(channel < power->chs)
  949. {
  950. pch = &power->pch[channel];
  951. uint16_t reg_close = power->pch[channel].info.close_delay;
  952. power->set_delay(pch->info.addr,pch->info.sch,reg,reg_close);
  953. }
  954. }
  955. break;
  956. case AC_3_SET_DELAY_CLOSE ... (AC_3_CHN_SET_SWITCH_STA_REG-1):
  957. {
  958. uint16_t channel = addr - AC_DC_SET_DELAY_CLOSE;
  959. if(channel < power->chs)
  960. {
  961. pch = &power->pch[channel];
  962. uint16_t reg_open = power->pch[channel].info.open_delay;
  963. power->set_delay(power->pch[channel].info.addr,power->pch[channel].info.sch,reg_open,reg);
  964. }
  965. }
  966. break;
  967. case AC_3_CHN_SET_SWITCH_STA_REG ... (AC_3_ALL_SET_SWITCH_REG -1):
  968. {
  969. uint16_t channel = addr - AC_DC_CHN_SET_SWITCH_STA_REG;
  970. if(channel < power->chs)
  971. {
  972. pch = &power->pch[channel];
  973. power->set_status(pch->info.addr,pch->info.sch,reg);
  974. }
  975. }
  976. break;
  977. case AC_3_ALL_SET_SWITCH_REG:
  978. {
  979. power->set_all_status(reg);
  980. }
  981. break;
  982. }
  983. }
  984. return(-2);
  985. }
  986. uint8_t cascade_read_slave(uint8_t addr)
  987. {
  988. memset(&slave_info.chache->info,0,sizeof(slave_info_t));
  989. slave_info.read_addr = addr;
  990. }
  991. int cascade_get_dlist(dev_list_t *dl)
  992. {
  993. int i,cnt=0;
  994. slave_t *sl=NULL;
  995. if(!dl) {
  996. return -1;
  997. }
  998. sl = (slave_t*)malloc(sizeof(slave_t)*(POWER_CASCADE_MAX+1));
  999. if(!sl) {
  1000. return -1;
  1001. }
  1002. for(i=0; i<=POWER_CASCADE_MAX; i++) {
  1003. if(slave_info.slaves[i].addr>=0) {
  1004. sl[cnt++] = slave_info.slaves[i];
  1005. }
  1006. }
  1007. dl->slave = sl;
  1008. dl->cnt = cnt;
  1009. LOGD("____dev cnt: %d\n", cnt);
  1010. }
  1011. int cascade_free_dlist(dev_list_t *dl)
  1012. {
  1013. if(!dl) {
  1014. return -1;
  1015. }
  1016. free(dl->slave);
  1017. return 0;
  1018. }
  1019. int cascade_lock(int flag)
  1020. {
  1021. cascade_handle_t *h=&slave_info;
  1022. if(flag) {
  1023. lock_on(h->lock);
  1024. }
  1025. else {
  1026. lock_off(h->lock);
  1027. }
  1028. return 0;
  1029. }