SmartPDCode/485/src/cascade_slave.c

#include "modbus.h"
#include "common.h"
#include "list.h"
#include "switch_ctrl.h"
#include "cascade.h"
#include "sqlite_handle.h"
#include "modbus_handle.h"



#define DEV_CHN_REG                 (4000)  
#define OUT_INFO_REG                (4001)     
#define IN_TOTAL_REG                (4768)  
#define TEM_HUMAN_REG               (4777)       
#define CHN_SWITCH_REG              (4779)
#define CHN_OPEN_DLA_REG            (4843)
#define CHN_CLOSE_DLA_REG           (4907)
#define CHN_SET_OPEN_DLA_REG        (5000)
#define CHN_SET_CLOSE_DLA_REG       (5064)
#define CHN_SET_SWITCH_STA_REG      (5128)
#define ALL_SET_SWITCH_REG          (5192)





#define For85_DEV_CHN_REG            (4000)
#define For85_ALL_OVER               (4100)
#define For85_SET_ADDR               (4101)
#define For85_SET_RECOVERY           (4102)
#define For85_SET_REBOOT             (4103)
#define For85_CONESUMER_CLEAR        (4104)


enum{
    D_For85_DEV_CHN_REG=0,
};


static mmap_modbus_t For85[] = {
    [D_For85_DEV_CHN_REG       ]{.offset = For85_DEV_CHN_REG        },
};


enum{
    TYPE_U16,
    TYPE_U32
};


// enum {
//     DS_R_DEV_CHN = 0,
//     DS_R_OUT_INFO,
//     DS_R_IN_TOTAL,
//     DS_R_TEMP_HUM,
//     DS_R_SWITCH_STA,
//     DS_R_OPEN_DELAY,
//     DS_R_CLOSE_DELAY,
//     DS_W_OPEN_DELAY,
//     DS_W_CLOSE_DELAY,
//     DS_W_CHN_SWITCH_STA,
//     DS_W_ALL_CHN_STA
// };


// #define TREE_DEV_CHN_REG                (6000)  
// #define TREE_INPUT_A_REG                (6001)     
// #define TREE_INPUT_B_REG                (6009)  
// #define TREE_INPUT_C_REG                (6017)       
// #define TREE_CHN_TOTAL_REG              (6025)
// #define TREE_CHN_PH_REG                 (6665)
// #define TREE_TEMP_HUM_REG               (8585)
// #define TREE_CHN_SWITCH_STA_REG         (8587)
// #define TREE_CHN_OPEN_DLA_REG           (8651)
// #define TREE_CHN_CLOSE_DLA_REG          (8715)
// #define TREE_CHN_SET_OPEN_DLA_REG       (9000)
// #define TREE_CHN_SET_CLOSE_DLA_REG      (9064)
// #define TREE_CHN_SET_SWITCH_STA_REG     (9128)
// #define TREE_ALL_SET_SWITCH_REG         (9192)

// enum {
//     TREE_R_DEV_CHN,
//     TREE_R_INPUT_ALL_A,
//     TREE_R_INPUT_ALL_B,
//     TREE_R_INPUT_ALL_C,
//     TREE_R_CHN_TOTAL,
//     TREE_R_CHN_PH_INFO,
//     TREE_R_TEMP_HUM,
//     TREE_R_SWITCH_STA,
//     TREE_R_OPEN_DELAY,
//     TREE_R_CLOSE_DELAY,
//     TREE_W_OPEN_DELAY,
//     TREE_W_CLOSE_DELAY,
//     TREE_W_CHN_SWITCH_STA,
//     TREE_W_ALL_CHN_STA
// };


// #define DEV_CHN_REG                     (4000)
// #define SWITCH_STATUE_REG               (4001)
// #define POWER_INFO_REG                  (4002)
// #define TEPM_HUM_REG                    (4016)
// #define SENCOR_STATUS                   (4018)

// enum{
//     IP_DEV_CHN,
//     IP_SWITCH_STATUE,
//     IP_POWER_INFO,
//     IP_TEMP_HUM,
//     IP_SENCOR_STATUS,
// };



static inline GlobalDeviceManager* get_dm(void)
{
    return &__globalDeviceManage;
}
// static inline GlobalDeviceManager* get_dm2(void)
// {
//     return &__globalDeviceManage2;
// }

// static mmap_modbus_t modbus_single[] = {
//     [DS_R_DEV_CHN       ]{.offset = DEV_CHN_REG             },
//     [DS_R_OUT_INFO      ]{.offset = OUT_INFO_REG            },
//     [DS_R_IN_TOTAL      ]{.offset = IN_TOTAL_REG            },
//     [DS_R_TEMP_HUM      ]{.offset = TEM_HUMAN_REG           },
//     [DS_R_SWITCH_STA    ]{.offset = CHN_SWITCH_REG          },
//     [DS_R_OPEN_DELAY    ]{.offset = CHN_OPEN_DLA_REG        },
//     [DS_R_CLOSE_DELAY   ]{.offset = CHN_CLOSE_DLA_REG       },
//     [DS_W_OPEN_DELAY    ]{.offset = CHN_SET_OPEN_DLA_REG    },
//     [DS_W_CLOSE_DELAY   ]{.offset = CHN_SET_CLOSE_DLA_REG   },
//     [DS_W_CHN_SWITCH_STA]{.offset = CHN_SET_SWITCH_STA_REG  },
//     [DS_W_ALL_CHN_STA   ]{.offset = ALL_SET_SWITCH_REG      },
// };

// static mmap_modbus_t modbus_three[] = {
//     [TREE_R_DEV_CHN         ]{.offset = TREE_DEV_CHN_REG},
//     [TREE_R_INPUT_ALL_A     ]{.offset = TREE_INPUT_A_REG       },
//     [TREE_R_INPUT_ALL_B     ]{.offset = TREE_INPUT_B_REG       },
//     [TREE_R_INPUT_ALL_C     ]{.offset = TREE_INPUT_C_REG       },
//     [TREE_R_CHN_TOTAL       ]{.offset = TREE_CHN_TOTAL_REG     },
//     [TREE_R_CHN_PH_INFO     ]{.offset = TREE_CHN_PH_REG        },
//     [TREE_R_TEMP_HUM        ]{.offset = TREE_TEMP_HUM_REG      },
//     [TREE_R_SWITCH_STA      ]{.offset = TREE_CHN_SWITCH_STA_REG},
//     [TREE_R_OPEN_DELAY      ]{.offset = TREE_CHN_OPEN_DLA_REG  },
//     [TREE_R_CLOSE_DELAY     ]{.offset = TREE_CHN_CLOSE_DLA_REG },
//     [TREE_W_OPEN_DELAY      ]{.offset = TREE_CHN_SET_OPEN_DLA_REG},
//     [TREE_W_CLOSE_DELAY     ]{.offset = TREE_CHN_SET_CLOSE_DLA_REG},
//     [TREE_W_CHN_SWITCH_STA  ]{.offset = TREE_CHN_SET_SWITCH_STA_REG},
//     [TREE_W_ALL_CHN_STA     ]{.offset = TREE_ALL_SET_SWITCH_REG }
// };

typedef struct { 
    modbus_mapping_t    *map;
}slave_handle_t;

static slave_handle_t slHandle;


modbus_mapping_t    *cascade_slave_map()
{
    return slHandle.map;
}


int cascade_slave_init(void)
{
    slave_handle_t *sh=&slHandle;
    GlobalDeviceManager* mgr=get_dm();
    if(sh->map)
    {
        free(sh->map);
        sh->map = 0;
    }
    sh->map = modbus_mapping_new_start_address(0,0,0,0,For85_DEV_CHN_REG,200,0,0);     //3000 ge
    For85[D_For85_DEV_CHN_REG].addr = &mgr->for85_data.addr;
    return 0;
}

void cascade_slave_read(uint32_t addr,uint32_t lenth)
{
    slave_handle_t *sh=&slHandle;

    switch (addr)
    {
        case For85_DEV_CHN_REG ... For85_ALL_OVER:
        {
            uint16_t *base_addr = (uint16_t *)For85[D_For85_DEV_CHN_REG].addr;
            uint32_t step = addr - sh->map->start_registers;
            base_addr = base_addr + (addr - For85[D_For85_DEV_CHN_REG].offset);
            uint16_t *map_addr = (uint16_t *)&(sh->map->tab_registers[step]);
            if(lenth < 126)
            {
                memcpy(map_addr, base_addr,2*lenth);
            }
        }
        break;
    }
}

void cascade_slave_write(void* manager,uint32_t addr,uint16_t val)
{
    GlobalDeviceManager* mgr=get_dm();
    switch(addr)
    {
        case For85_SET_ADDR:
        {
            dev_set_485_saddr(mgr->db,val,mgr->_global_device_info);
            Modbus_Manger *modbus_manger = (Modbus_Manger *)(manager);
            pthread_mutex_lock(&modbus_manger->mutex);
            modbus_set_slave(modbus_manger->mb, addr);
            pthread_mutex_unlock(&modbus_manger->mutex);
        }
        break;
        case For85_SET_RECOVERY:
        {
            sqlite3_close(mgr->db);
            system("cp -r /opt/pdu_dat_bak.db /opt/pdu_dat.db");

            system("reboot -f");
        }
        break;
        case For85_SET_REBOOT:
        {
            sqlite3_close(mgr->db);
            system("reboot -f");
        }
        break;
        case For85_CONESUMER_CLEAR:
        {
            mgr->_global_device_info->consumer = 0.0;
        }
        break;
        default:
        break;
    }
}