SmartPDCode/GD32F427/app/cascade/cascade.c

#include "bsp_cas.h"
#include "cascade.h"
#include "modbus.h"
#include "stdio.h"
#include "string.h"
#include "power.h"
#include "paras.h"
#include "cfg.h"
#include "sensor.h"



#define REGS(x)    (((x)+(x)%2)/2)


typedef void * handle_t;

typedef struct {
    mb_inst_t  *hinst;
    uint8_t    mode;
    uint8_t    type;
    uint8_t    quit;
    
}mb_handle_t;

typedef struct {
		union {
		md_ac_dc_t ac_dc;
		md_3_ac_t  ac_3; 
	}data;
}north_data_t;

typedef struct cascade_saddr{
    uint8_t      addr;
    uint16_t     channels;
    power_ch_new_t   ch[POWER_SLAVE_CH_MAX];
}slave_info_t;

typedef union{
	slave_info_t			info;
	north_data_t 			north;
}cascade_data_cache;


typedef struct cascade_info{
	uint8_t         switch_flag;
	uint8_t  				saddr;
	uint8_t         read_addr;
	uint8_t 				md_type;
	uint32_t        bund;
	uint8_t         quit;
	SemaphoreHandle_t 				  xMutex;
	slave_t         slaves[POWER_CASCADE_MAX+1];
	cmd_data_t    cmd;
	cascade_data_cache *chache;
	mb_inst_t   		*rtu_hist;
	mb_inst_t  			*tcp_hinst;
	mb_backend_param_t param;
}cascade_handle_t;



static int sendlen=0;																
static cascade_handle_t slave_info = {0};		
static TCM_DATA cascade_data_cache cache = {0};
static mb_cascade_fun_t func = {0};							



const mb_cb_table_t mb_table = {
    .read_disc = mb_port_read_disc,      						
    .read_coil = mb_port_read_coil,      						
    .write_coil = mb_port_write_coil,    						
    .read_input = mb_port_read_input,    						
    .read_hold = mb_port_read_hold,      						
    .write_hold = mb_port_write_hold,    						
};






static int 					mb_write_read(cascade_handle_t *cas, int addr, data_t *wd, data_t *rd);
static int 					master_query(cascade_handle_t *cas);
static void 				slave_func(uint16_t reg,void *r_w_data,uint32_t lenth);
static int 					slave_get_info(cascade_handle_t *cas);
static int 					master_cmd(cascade_handle_t *cas,uint8_t cur_dev_addr ,cmd_data_t *cmd);
static void 				slave_rm(uint8_t addr);
static void 				memswap(uint8_t *buf, int len);
static void *       my_memcpy_byte(void *dst, const void *src, int n);
static uint8_t 			master_scan(cascade_handle_t *cas);
static int 					_mb_write(cascade_handle_t *cas, int addr, data_t *d);
static int 					_mb_read(cascade_handle_t *cas, int addr, data_t *d);



static void* 				off_on_thread(void *arg);									//??????????
	


static void memswap(uint8_t *buf, int len)

{
    int i;
    uint8_t tmp;

    for(i=0; i<len; i+=2) {
        tmp = buf[i];
        buf[i] = buf[i+1];
        buf[i+1] = tmp;
    }
}

static void slave_rm(uint8_t addr)
{
	if(addr > 0  && addr < POWER_SLAVE_CH_MAX)
	{
		slave_info.slaves[addr].addr = 0;
		slave_info.slaves[addr].err = 0;
	}
}



static int cas_read(uint8_t addr,uint16_t reg,uint16_t *data,uint16_t cnt)
{
	int r = 0;
	cascade_handle_t *_info = &slave_info;
	if(xSemaphoreTake(_info->xMutex, portMAX_DELAY)== pdTRUE)
	{
		mb_set_slave(_info->rtu_hist, addr);
		r = mb_read_regs(_info->rtu_hist, reg, cnt, data);
		xSemaphoreGive(_info->xMutex);
	}
	return r;
}


static int cas_write(uint8_t addr,uint16_t reg,uint16_t *data,uint16_t cnt)
{
	int r = 0;
	cascade_handle_t *_info = &slave_info;
	if(xSemaphoreTake(_info->xMutex, portMAX_DELAY)== pdTRUE)
	{
		mb_set_slave(_info->rtu_hist, addr);
		r = mb_write_regs(_info->rtu_hist, reg, cnt, data);
		xSemaphoreGive(_info->xMutex);
	}
	return r;
}





static uint8_t master_scan(cascade_handle_t *cas)
{
#if SUPPORT_CASCADE_QMODBUS
	int r = 0;
	static uint8_t slave_addr = 1;
	if(slave_addr > POWER_CASCADE_MAX)
	{
		slave_addr = 1;
	}
	if(cas->slaves[slave_addr].addr == 0)
	{
		//scan
		uint16_t value = 0;
		cas_read(slave_addr,CASCADE_REG_SCAN,&value,1);
		if(r > 0)
		{
			LOGD("scan slave addr %d !!!\n",slave_addr);
			cas->slaves[slave_addr].addr = slave_addr;
			cas->slaves[slave_addr].err = 0;
		}
	}
	slave_addr++;
#endif
}



static int slave_get_info(cascade_handle_t *cas)
{
#if SUPPORT_CASCADE_QMODBUS
	slave_info_t *info = &cas->chache->info;
	power_handle_new_t *p_handle = power_get_all();
	info->channels = p_handle->chs;
	for(int i=0; i < info->channels;i++)
	{
		info->ch[i] = p_handle->pch[i];
	}
	LOGD("slave will send %d channels to master!!!!\n",info->channels);
#endif
	return 0;
}


static void slave_func(uint16_t reg,void *r_w_data,uint32_t lenth)
{
#if SUPPORT_CASCADE_QMODBUS
	cmd_data_t *cmd=NULL;
	power_handle_new_t *p_handle = power_get_all();
	switch (reg)
	{
		case CASCADE_REG_SCAN:

		break;
		case CASCADE_REG_WRITE:
		{
			
			cmd = (cmd_data_t*)(r_w_data);
      if(cmd->cmd>=CASCADE_CMD_GET_INFO) {
					memcpy(&slave_info.cmd,r_w_data,sizeof(cmd_data_t));
					sendlen = slave_info.cmd.c_m.sendlen_offset;
      }

      
			switch(cmd->cmd)
			{
				case CASCADE_CMD_OPEN:
        case CASCADE_CMD_CLOSE:
				{
//					cmd_data_t *pcmd=malloc(sizeof(cmd_data_t));
//          if(pcmd) {
//            *pcmd = *cmd;
//						pthread_create(&id,NULL,off_on_thread,pcmd);
//						pthread_detach(id);
//          }
				}
					break;
        case CASCADE_CMD_OPEN_NF:
        case CASCADE_CMD_CLOSE_NF:
				{
				}
					break;
        case CASCADE_CMD_SAVE:
        case CASCADE_CMD_SAVE3:
				{
				}
					break;
				case CASCADE_CMD_BREAKER_SAVE_ADD:
				{
				}
					break;
				case CASCADE_CMD_BREAKER_SAVE_UPDATE:
				{
				}
					break;
				case CASCADE_CMD_BREAKER_SAVE_DELETE:
				{
				}
					break;
			}
		}
		break;
		case CASCADE_REG_READ:
		{
			cmd = &slave_info.cmd;
			
			switch(cmd->cmd)
			{
				case CASCADE_CMD_GET_INFO:
				{
					
					uint8_t * base_addr = (uint8_t *)&p_handle->pch[0];
					memcpy(r_w_data,base_addr+sendlen,lenth*2);
					memswap(r_w_data,lenth*2);
					LOGD("____read_____ readlen = %d,sendlen = %d power_ch_t size=%d\n",lenth,sendlen,sizeof(power_ch_t));
				}
					break;
				case CASCADE_CMD_QUERY_CH:
				{
					uint8_t * base_addr = (uint8_t *)&p_handle->pch[0];
					memcpy(r_w_data,base_addr+sendlen,lenth*2);
					memswap(r_w_data,lenth*2);
				}
					break;
				case CASCADE_CMD_BREAKER_QUERY:
					break;
        case CASCADE_CMD_QUERY_VOL:break;
        case CASCADE_CMD_QUERY_CUR:break;
        case CASCADE_CMD_QUERY_PWR:break;
        case CASCADE_CMD_QUERY_PWRQ:break;
        case CASCADE_CMD_QUERY_HIS:break;
        case CASCADE_CMD_QUERY_TOTAL:break;
        case CASCADE_CMD_QUERY_TOTAL_PWR:break;
        case CASCADE_CMD_BREAKER_GET_INFO:break;
			}
			//sendlen += lenth*2;
		}
		break;
		default:
		{
			
		}
		break;
	}
#endif
}

static int _mb_write(cascade_handle_t *cas, int addr, data_t *d)
{

	int i = 0,r=0,timeout=0;
#if SUPPORT_CASCADE_QMODBUS
  int wl,xlen,wlen=0,oncelen=250;
	uint8_t retry = 5;
	uint8_t buff[MB_BUF_SIZE+100];
	if(d->dlen<=0) {
        return -1;
  }

		while(1)
		{
			 if(wlen+oncelen>d->dlen) {
				xlen = d->dlen-wlen;
			 } else 
			 {
				 xlen = oncelen;
			 }
			xlen += xlen%2;
			memcpy(buff, d->data+wlen, xlen);
			memswap(buff,xlen%2+xlen);
			wl = cas_write(addr,CASCADE_REG_WRITE,(uint16_t*)buff,xlen/2);
			if(wl<=0) {
				LOGD("___ _mb_write failed, addr: %d, reg: %d, cnt: %d, %s, retry: %d   errno = %d \n", addr, CASCADE_REG_WRITE, xlen/2,"write failed",i+1,wl);
				if(addr >0 && addr < POWER_SLAVE_CH_MAX)
				{
					slave_info.slaves[addr].err ++;
					if(slave_info.slaves[addr].err > 5)
					{
						slave_rm(addr);
					}
				}
				r = -1; 
				break;
			}else
			{
				slave_info.slaves[addr].err = 0;
				r = 0;
			}
			if(wlen+wl*2>=d->dlen) {
				break;
			}else {
				xlen = wl*2;
			}
			wlen += xlen;
		}
	return r;
#endif
}
static int _mb_read(cascade_handle_t *cas, int addr, data_t *d)
{
    int i=0,r=0,finish=0,timeout=0;
#if SUPPORT_CASCADE_QMODBUS
    int rl,xlen,rlen=0,oncelen=250;
		uint8_t retry = 5;
    uint16_t buff[MB_BUF_SIZE];	
    if(d->dlen<=0) {
        return -1;
    }
		while(1) {
				if(rlen+oncelen>d->dlen) {
					 xlen = d->dlen-rlen;
				}else{
					 xlen = oncelen;
				}
				xlen += xlen%2;
				rl = cas_read(addr,CASCADE_REG_READ,buff,xlen/2);

				if(rl<=0) {
					LOGD("___ _mb_read failed, %s, rlen: %d, retry: %d\n", "read error", rlen, i+1);
					if(addr >0 && addr < POWER_SLAVE_CH_MAX)
					{
						cas->slaves[addr].err ++;
						if(cas->slaves[addr].err > 5)
						{
								slave_rm(addr);
						}
					}
					r = -1; break;
				}else
				{
					cas->slaves[addr].err =0;
				}
				if(rlen+rl*2>=d->dlen) {
					xlen = d->dlen-rlen;
					finish = 1;
				}else 
				{
					xlen = rl*2;
				}

				memcpy((char*)d->data+rlen, buff, xlen);
				rlen += xlen;
				if(finish) {
					 r = 0;
					 break;
				}
			}
#endif
		return r;
}


static int mb_write_read_n(cascade_handle_t *cas, int addr, data_t *wd, data_t *rd)
{
	int i=0,r=0,finish=0,timeout=0;
#if SUPPORT_CASCADE_QMODBUS
  int rl,xlen,rlen=0,oncelen=250;
	uint16_t buff[MB_BUF_SIZE];
	
	while(1) {

		cas->cmd.c_m.sendlen_offset = rlen;
		wd->dlen = sizeof(cmd_data_t);
		wd->data = (uint8_t*)&(cas->cmd);
		r = _mb_write(cas, addr,wd);

		if(rlen+oncelen>rd->dlen) {
			xlen = rd->dlen-rlen;
		}else{
			xlen = oncelen;
		}
		
		xlen += xlen%2;
		while(1)
		{
			rl = cas_read(addr,CASCADE_REG_READ,buff, xlen/2);
			
			if(rl<=0) {
				if(addr >0 && addr < POWER_SLAVE_CH_MAX) {
					cas->slaves[addr].err ++;
					LOGD("___ _mb_read failed, %s, rlen: %d, retry: %d  ernno=%d\n", "read error", rlen, cas->slaves[addr].err,rl);
					if(cas->slaves[addr].err > 5) {
						slave_rm(addr);
						goto fail;
					}
				}else {
					goto fail;
				}
			}else {
				cas->slaves[addr].err =0;
				break;
			}
		}
		if(rlen+rl*2>=rd->dlen) {
			xlen = rd->dlen-rlen;
			finish = 1;
		}else {
			xlen = rl*2;
		}
		if(xSemaphoreTake(cas->xMutex, portMAX_DELAY)== pdTRUE)
		{
				memcpy((char*)rd->data+rlen, buff, xlen);
				xSemaphoreGive(cas->xMutex);
		}
		rlen += xlen;
		if(finish) {
			r = 0;
			break;
		}
	}
#endif
fail:
	return r;	
}



static void* off_on_thread(void *arg)
{
#if SUPPORT_CASCADE_QMODBUS
	cascade_handle_t *cas=&slave_info;
	cmd_data_t *pcmd=(cmd_data_t*)arg;
	if(pcmd->cmd==CASCADE_CMD_OPEN) {
     //   LOGD("____ slave CASCADE_CMD_OPEN\n");
  }
   else {
   //     LOGD("____ slave CASCADE_CMD_CLOSE\n");
    }
	int flag=((pcmd->cmd==CASCADE_CMD_OPEN)?1:0);
	if(pcmd->chId == 0xff) {
		// all
	}else
	{
		//one
	}
	 if(pcmd->cmd==CASCADE_CMD_OPEN) {
     //   sprintf(temp,"$??$|$??$|$??$");
    }
    else {
     //   sprintf(temp,"$??$|$??$|$??$");
    }
		//data base
		free(pcmd);
//		pthread_exit(NULL);
#endif
}

static int master_cmd(cascade_handle_t *cas,uint8_t cur_dev_addr ,cmd_data_t *cmd)
{
    int i,r;
#if SUPPORT_CASCADE_QMODBUS
    data_t rdata,wdata;
		
    if(cur_dev_addr==0) {
        return -1;
    }

    switch(cmd->cmd) {
        case CASCADE_CMD_OPEN:
        case CASCADE_CMD_CLOSE:
        case CASCADE_CMD_SAVE:
        case CASCADE_CMD_SAVE3:
        case CASCADE_CMD_OPEN_NF:
        case CASCADE_CMD_CLOSE_NF:
        {
            LOGD("____ master CMD: %d\n", cmd->cmd);

            wdata.dlen = sizeof(cmd_data_t);
            wdata.data = (uint8_t*)cmd;
            r = _mb_write(cas, cur_dev_addr, &wdata);
        }
        break;

        case CASCADE_CMD_GET_INFO:
        {
            wdata.dlen = sizeof(cmd_data_t);
            wdata.data = (uint8_t*)cmd;


						uint16_t value = 0;
						r = cas_read(cur_dev_addr,4000,&value,1);//?????
						LOGD("r = %d  value=%d\n",r,value);
            if(r > 0)
						{
							uint8_t chanels = value & 0xff;
							if(chanels == 0 || chanels > 100)
							{
								cas->chache->info.channels = 0;
								LOGD("get slave channels %d!!!\n",chanels);
							}else
							{
								if(chanels >= POWER_SLAVE_CH_MAX)
										chanels = POWER_SLAVE_CH_MAX;
								cas->chache->info.channels = chanels;
                rdata.dlen = sizeof(power_ch_t)*cas->chache->info.channels;
								rdata.data = (uint8_t*)&(cas->chache->info.ch);
								r = mb_write_read_n(cas, cur_dev_addr, &wdata, &rdata);
								if(r==0) {

                }else
								{
									 LOGD("_____ master CASCADE_CMD_GET_INFO read failed\n");
								}
							}
						}
        }
        break;
        case CASCADE_CMD_BREAKER_GET_INFO:
        {

        }
        break;
        case CASCADE_CMD_BREAKER_SAVE_UPDATE:
        case CASCADE_CMD_BREAKER_SAVE_DELETE:
        case CASCADE_CMD_BREAKER_SAVE_ADD:
        {
        }
        break;
        default:
        cas->cmd = *cmd;
        r = 0;
    }
#endif
    return r;
}




uint8_t cascade_init(void)
{	
#if SUPPORT_CASCADE_QMODBUS
	paras_data_t* p_d = paras_get();
	memset(&slave_info,0,sizeof(slave_info));
	slave_info.quit = 1;
	slave_info.xMutex = xSemaphoreCreateMutex();
	slave_info.md_type = p_d->cas.mode;
	slave_info.chache = &cache;
	bsp_cas_init(p_d->cas.baud);
	
	mb_backend_param_t para ={0};
	para.rtu.baudrate = p_d->cas.baud;
	strcpy(para.rtu.dev,"usart1");
	slave_info.rtu_hist =  mb_create(MB_BACKEND_TYPE_RTU, &para);
	mb_connect(slave_info.rtu_hist);
	
	if(p_d->cas.mode == MB_MODE_SLAVE)
	{

		mb_set_slave(slave_info.rtu_hist,p_d->cas.addr);
		mb_set_cb_table(slave_info.rtu_hist,&mb_table);
		func.slave_func = slave_func;
		mb_set_cb_cascade(slave_info.rtu_hist, &func);
		memset(&slave_info.chache->north,0,sizeof(north_data_t));
	}else if(p_d->cas.mode == MB_MODE_MASTER)
	{
		memset(&slave_info.chache->info,0,sizeof(slave_info_t));	
	}else
	{
		slave_info.chache = 0;
		return -1;
	}
	slave_info.quit = 0;
	slave_info.read_addr = 1;
#endif
	return 0;
}


void cascade_reset_new(uint8_t mode,uint8_t addr,uint32_t baund)
{
#if SUPPORT_CASCADE_QMODBUS
	slave_info.switch_flag = 1;
	paras_data_t* p_d = paras_get();
	if(baund != p_d->cas.baud)
	{
		bsp_cas_reset(baund);
	}
	if(mode != slave_info.md_type)
	{
		if(mode == MB_MODE_MASTER)
		{
			slave_info.md_type = MB_MODE_MASTER;
			memset(&slave_info.chache->info,0,sizeof(slave_info_t));	
		}else
		{
			slave_info.md_type = MB_MODE_SLAVE;
			mb_set_slave(slave_info.rtu_hist,addr);
			memset(&slave_info.chache->north,0,sizeof(north_data_t));
		}
	}else
	{
		if(mode == MB_MODE_SLAVE)
		{
				mb_set_slave(slave_info.rtu_hist,addr);
		}
	}
	p_d->cas.addr = addr;
	p_d->cas.baud = baund;
	p_d->cas.mode = mode;
	paras_save();
	slave_info.switch_flag = 0;
	
#endif
	
}


void cas_scan_query(void)
{
	if(!slave_info.switch_flag)
	{
		if(slave_info.md_type == MB_MODE_MASTER)
		{
			master_scan(&slave_info);
		}else
		{
			paras_data_t* p_data = paras_get();
			sensor_all_t* sensor = sensor_get_data();
			power_handle_new_t *all = power_get_all();
      
			if(p_data->prod.type == PDU_AC_I1O1 || p_data->prod.type == PDU_DC_I1O1)
			{
				int channels = all->chs;
				slave_info.chache->north.data.ac_dc.dev_cnt = (p_data->prod.type << 8 | channels);
				int cnt = all->chs > POWER_SLAVE_CH_MAX ? POWER_SLAVE_CH_MAX : channels;

				for(int i = 0; i < cnt;i++)
				{
					slave_info.chache->north.data.ac_dc.power[i].voltage 		= all->pch[i].power[0].voltage *1000;
					slave_info.chache->north.data.ac_dc.power[i].current 		= all->pch[i].power[0].current *1000;
					slave_info.chache->north.data.ac_dc.power[i].power 			= all->pch[i].power[0].power *1000;
					slave_info.chache->north.data.ac_dc.power[i].consumer  	= all->pch[i].power[0].consump *1000;
					slave_info.chache->north.data.ac_dc.power[i].factor 		= all->pch[i].power[0].factor *1000;
					slave_info.chache->north.data.ac_dc.power[i].freq 			= all->pch[i].power[0].freq *1000;
					slave_info.chache->north.data.ac_dc.switch_stu[i] 			= all->pch[i].info.status;
					slave_info.chache->north.data.ac_dc.delay_open[i] 			= all->pch[i].info.open_delay;
					slave_info.chache->north.data.ac_dc.delay_close[i] 			= all->pch[i].info.close_delay;
				}

				slave_info.chache->north.data.ac_dc.power_all.all_consumer = all->total.all.consump *1000;
				slave_info.chache->north.data.ac_dc.power_all.all_current  = all->total.all.current *1000;
				slave_info.chache->north.data.ac_dc.power_all.all_power    = all->total.all.power *1000;
				slave_info.chache->north.data.ac_dc.power_all.all_voltage  = all->total.all.voltage *1000;

				slave_info.chache->north.data.ac_dc.temp = sensor->data[0].val[1].value;				
				slave_info.chache->north.data.ac_dc.humity = sensor->data[0].val[0].value;
			}else
			{
				int channels = all->chs > 0 ? all->chs: 0;
				slave_info.chache->north.data.ac_3.dev_cnt = (p_data->prod.type << 8 | channels);
				for(int i = A_P; i <= C_P;i++)
				{
					slave_info.chache->north.data.ac_3.ac_3_all_pw[i].consumer = all->total.all_l[i].consump *1000;
					slave_info.chache->north.data.ac_3.ac_3_all_pw[i].current  = all->total.all_l[i].current *1000;
					slave_info.chache->north.data.ac_3.ac_3_all_pw[i].power    = all->total.all_l[i].power *1000;
					slave_info.chache->north.data.ac_3.ac_3_all_pw[i].voltage  = all->total.all_l[i].voltage *1000;
				}
				int cnt = all->chs > POWER_SLAVE_CH_MAX ? POWER_SLAVE_CH_MAX : channels;
				for(int i = 0; i < cnt;i++)
				{
					for(int j = A_P; j <= C_P;j++)
					{
						slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_consumer = all->pch[i].power[j].consump * 1000;
						slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_current  = all->pch[i].power[j].current * 1000;
						slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_power    = all->pch[i].power[j].power * 1000;
						slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_voltage  = all->pch[i].power[j].voltage * 1000;
						slave_info.chache->north.data.ac_3.ac_3_chn_p[i][j].p_status   = all->pch[i].info.status;		
					}
				}	
				slave_info.chache->north.data.ac_3.temp = sensor->data[0].val[1].value;				
				slave_info.chache->north.data.ac_3.humity = sensor->data[0].val[0].value;
				for(int i = 0; i < cnt;i++)
				{
					slave_info.chache->north.data.ac_3.delay_open[i] = all->pch[i].info.open_delay;
					slave_info.chache->north.data.ac_3.delay_close[i] = all->pch[i].info.close_delay;
				}
			}
		}
	}
}

void cas_query(void)
{
	if(!slave_info.switch_flag)
	{
		 if(slave_info.md_type==MB_MODE_MASTER) { 
			 //master
		 }else
		 {
			 mb_slave_fsm(slave_info.rtu_hist);
		 }
	}
	vTaskDelay(20);
}



int cascade_request(cmd_data_t *cmd)
{
	master_cmd(&slave_info,1,cmd);
	return 0;
}


int mb_port_read_disc(u16 addr, u8 *pbit)//??????, ?? : 0-??, -2-????
{
    MB_ASSERT(pbit != NULL);
    
    return(-2);
}

int mb_port_read_coil(u16 addr, u8 *pbit)//???, ?? : 0-??, -2-????
{
    MB_ASSERT(pbit != NULL);
    
    return(-2);
}

int mb_port_write_coil(u16 addr, u8 bit)//???, ?? : 0-??, -2-????, -4-????
{
    return(-2);
}

int mb_port_read_input(u16 addr, u16 *preg)//??????, ?? : 0-??, -2-????
{
    MB_ASSERT(preg != NULL);
    
    return(-2);
}

int mb_port_read_hold(u16 addr, u16 *preg)//??????, ?? : 0-??, -2-????
{
    MB_ASSERT(preg != NULL);
		uint16_t *data = NULL;
    if( AC_DC_DEV_CHN_REG <= addr &&  addr <= AC_DC_DRY_REG)
		{
			data = (uint16_t*)(&slave_info.chache->north.data.ac_dc);
			uint32_t offset = addr - AC_DC_DEV_CHN_REG;
			*preg = *(data+offset);
			return 0;
		}
		if(AC_3_DEV_CHN_REG <= addr && addr <= AC_3_DRY_REG)
		{
			data = (uint16_t*)(&slave_info.chache->north.data.ac_3);
			uint32_t offset = addr - AC_3_DEV_CHN_REG;
			*preg = *(data+offset);
			return 0;
		}	
		return(-2);
}

int mb_port_write_hold(u16 addr, u16 reg)
{
  power_handle_new_t *power = power_get_all();
		
	power_ch_new_t * pch = NULL;
	
	if(AC_DC_SET_DELAY_OPEN <= addr && addr <= AC_DC_ALL_SET_SWITCH_REG)
	{
		switch(addr)
		{
			case AC_DC_SET_DELAY_OPEN ... (AC_DC_SET_DELAY_CLOSE-1):
			{
				uint16_t channel = addr - AC_DC_SET_DELAY_OPEN;
				if(channel < power->chs)
				{
					pch = &power->pch[channel];
					uint16_t reg_close = power->pch[channel].info.close_delay;
					power->set_delay(pch->info.addr,pch->info.sch,reg,reg_close);
				}
			}
			break;
			case AC_DC_SET_DELAY_CLOSE ...(AC_DC_CHN_SET_SWITCH_STA_REG - 1):
			{
				uint16_t channel = addr - AC_DC_SET_DELAY_CLOSE;
				if(channel < power->chs)
				{
					pch = &power->pch[channel];
					uint16_t reg_open = power->pch[channel].info.open_delay;
					power->set_delay(power->pch[channel].info.addr,power->pch[channel].info.sch,reg_open,reg);
				}				
			}
			break;
			case AC_DC_CHN_SET_SWITCH_STA_REG ... (AC_DC_ALL_SET_SWITCH_REG-1):
			{
				uint16_t channel = addr - AC_DC_CHN_SET_SWITCH_STA_REG;
				if(channel < power->chs)
				{
					pch = &power->pch[channel];
					power->set_status(pch->info.addr,pch->info.sch,reg);
				}
			}
			break;
			case AC_DC_ALL_SET_SWITCH_REG:
			{
				power->set_all_status(reg);
			}
			break;
		}
		return 0;
	}
	
	if(AC_3_SET_DELAY_OPEN <= addr && addr <= AC_3_ALL_SET_SWITCH_REG )
	{
		switch(addr)
		{
			case AC_3_SET_DELAY_OPEN ... (AC_3_SET_DELAY_CLOSE-1):
			{
				uint16_t channel = addr - AC_DC_SET_DELAY_OPEN;
				if(channel < power->chs)
				{
					pch = &power->pch[channel];
					uint16_t reg_close = power->pch[channel].info.close_delay;
					power->set_delay(pch->info.addr,pch->info.sch,reg,reg_close);
				}
			}
			break;
			case AC_3_SET_DELAY_CLOSE ... (AC_3_CHN_SET_SWITCH_STA_REG-1):
			{
				uint16_t channel = addr - AC_DC_SET_DELAY_CLOSE;
				if(channel < power->chs)
				{
					pch = &power->pch[channel];
					uint16_t reg_open = power->pch[channel].info.open_delay;
					power->set_delay(power->pch[channel].info.addr,power->pch[channel].info.sch,reg_open,reg);
				}					
			}
			break;
			case AC_3_CHN_SET_SWITCH_STA_REG ... (AC_3_ALL_SET_SWITCH_REG -1):
			{
				uint16_t channel = addr - AC_DC_CHN_SET_SWITCH_STA_REG;
				if(channel < power->chs)
				{
					pch = &power->pch[channel];
					power->set_status(pch->info.addr,pch->info.sch,reg);
				}
			}
			break;
			case AC_3_ALL_SET_SWITCH_REG:
			{
				power->set_all_status(reg);		
			}
			break;
		}
	}
	
	return(-2);
}