main.c 48 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632
  1. #include "gd32e23x.h"
  2. #include "systick.h"
  3. #include <stdio.h>
  4. #include "main.h"
  5. #include "Fwdgt.h"
  6. #include "mb.h"
  7. #include "Led.h"
  8. #include "Key.h"
  9. #include "cfg.h"
  10. #include "gd32e23x_fmc.h"
  11. #include "string.h"
  12. #include "Timer.h"
  13. #include "Fwdgt.h"
  14. #include "stdbool.h"
  15. #include "At24cxx.h"
  16. #include "Sn74hc573.h"
  17. #include "Relay.h"
  18. #include "ReadEeprom.h"
  19. #include "Uart1.h"
  20. #include "Hlw8110.h"
  21. #include "key_io.h"
  22. #include "Flash.h"
  23. #include "board_cfg.h"
  24. AC_Output_struct_Reg AC3PPDU_Output[Output_ChN_default + 2] = {0};
  25. AC3PPDU_RELAY_Para_Reg AC3PPDU_RL_time[Output_ChN_default + 2] = {0};
  26. AC3PPDU_RELAY_Para_Reg AC3PPDU_RL_N_time;
  27. static uint8_t AC3PPDU_SlaveAddress = 0x00;
  28. uint16_t Devid_IDChalNum = 0;
  29. bool RL_Allon_flag = false;
  30. bool RL_Alloff_flag = false;
  31. bool Start_Read_Flag = false;
  32. uint16_t CurrentAddr = 0;
  33. uint8_t flash_flag = 0;
  34. uint32_t AC3PPDU_Modbus_Reg[AC3PPDU_Modbus_Reg_len] = {0};
  35. uint8_t AC3PPDU_active_chn = Output_ChN_default;
  36. information_t infomation;
  37. uint32_t hlw8110_base[Output_ChN_default + 1] = {0}; //add by liyi
  38. uint8_t Wr_eeprom_cnt = 0;
  39. uint8_t RL_begin_delay_flag[Output_ChN_default+1] = {0x00};
  40. uint8_t RL_end_delay_flag[Output_ChN_default+1] = {0x00};
  41. uint8_t RL_ON_flag[Output_ChN_default+1] = {0x00};
  42. uint8_t RL_OFF_flag[Output_ChN_default+1] = {0x00};
  43. uint8_t RL_last_state[Output_ChN_default+1] = {0x00};
  44. uint8_t RL_now_state[Output_ChN_default+1] = {0x00};
  45. uint8_t RL_Func_statu[Output_ChN_default + 1] = {0x00};
  46. uint8_t RL_All_Func = 0x0;
  47. uint32_t normal_running_time = 0;
  48. #if SUPPORT_ZERO_LINE
  49. uint8_t RL_N_begin_delay_flag = 0x0; // add by liyi
  50. uint8_t RL_N_end_delay_flag = 0x0; // add by liyi
  51. uint8_t RL_N_ON_flag = 0x0; // add by liyi
  52. uint8_t RL_N_OFF_flag = 0x0; // add by liyi
  53. uint8_t RL_N_last_state = 0x0; // add by liyi
  54. uint8_t RL_N_now_state = 0x0; // add by liyi
  55. #endif
  56. uint8_t AC3PPDU_Vmax_LTen_flag[Output_ChN_default+1] = {0x01};
  57. uint8_t AC3PPDU_Vmin_LTen_flag[Output_ChN_default+1] = {0x01};
  58. uint8_t AC3PPDU_Imax_LTen_flag[Output_ChN_default+1] = {0x01};
  59. uint8_t AC3PPDU_Wmax_LTen_flag[Output_ChN_default+1] = {0x01};
  60. uint8_t AC3PPDU_kWhmax_LTen_flag[Output_ChN_default+1] = {0x01};
  61. bool orderFlag[Output_ChN_default] ={0};
  62. bool orderFlag_N = 0;
  63. uint32_t AC_BASE[4] = {0};
  64. META_DATA_S meta_data = {0};
  65. uint8_t write_kwh2Eeprom_flag = 0;
  66. uint8_t detection_value = 0;
  67. extern float hlw8110_store[Output_ChN_default + 1];
  68. extern uint32_t Modbus_Wr_buff[Mb_Wcmd_Width][Mb_Wcmd_len];
  69. extern uint32_t RL_N_delay_cnt; // add by liyi
  70. extern uint32_t RL_N_delay_Limit; // add by liyi
  71. extern uint32_t RL_delay_Limit[Output_ChN_default + 1];
  72. static void MODbus_CMD_New(void);
  73. static void Fault_state_process(uint8_t ch_x);
  74. static void break_2_boot_upgreade(void)
  75. {
  76. meta_data.errno = 0;
  77. meta_data.operation_flag = 1;
  78. meta_data.recent_running_time = normal_running_time;
  79. flash_erase_meta();
  80. flash_write_meta(&meta_data);
  81. __disable_irq();
  82. //__set_FAULTMASK(1);
  83. NVIC_SystemReset();
  84. }
  85. static void app_init(META_DATA_S *meta)
  86. {
  87. flash_get_meta_data(meta);
  88. nvic_vector_table_set(NVIC_VECTTAB_FLASH,meta->rom_addr - NVIC_VECTTAB_FLASH);
  89. __enable_irq();
  90. }
  91. static bool select_channel(uint8_t ch_x)
  92. {
  93. if(ch_x == 0)
  94. return false;
  95. switch(ch_x)
  96. {
  97. case CH1_out:
  98. {
  99. SEL_0_H;
  100. SEL_1_H;
  101. SEL_2_H;
  102. }
  103. break;
  104. case CH2_out:
  105. {
  106. SEL_0_L;
  107. SEL_1_H;
  108. SEL_2_H;
  109. }
  110. break;
  111. case CH3_out:
  112. {
  113. SEL_0_H;
  114. SEL_1_L;
  115. SEL_2_H;
  116. }
  117. break;
  118. default:
  119. return false;
  120. }
  121. return true;
  122. }
  123. void hlw8110_init(uint8_t ch_x)
  124. {
  125. if(select_channel(ch_x) == false)
  126. return;
  127. Init_HLW8110();
  128. }
  129. static void check_jlink()
  130. {
  131. #if SUPPORT_RELAY_CTRL
  132. #if SUPPORT_KEY_CTRL
  133. uint8_t test = false;
  134. uint8_t rst = false;
  135. #endif
  136. if(Chk_Jlink_conn() == false)
  137. {
  138. #if SUPPORT_KEY_CTRL
  139. rst = get_rst();
  140. test = get_test();
  141. #if SUPPORT_DETECTION
  142. if(detection_value == false) // duan lu qi shi fou zai xian
  143. {
  144. for(int i = 0; i < Output_ChN_default;i++)
  145. {
  146. AC3PPDU_RL_time[i + CH1_out].LT_state &=0xffffff7e;
  147. orderFlag[i]=true;
  148. }
  149. }else
  150. #endif
  151. {
  152. if(rst != test) //shou dong kai guan
  153. {
  154. if(rst)
  155. {
  156. for(int k = 0; k < Output_ChN_default;k++)
  157. {
  158. AC3PPDU_RL_time[k + CH1_out].LT_state &= 0xffffff7e;
  159. orderFlag[k]=true;
  160. }
  161. }else
  162. {
  163. for(int k = 0; k < Output_ChN_default;k++)
  164. {
  165. AC3PPDU_RL_time[k + CH1_out].LT_state &= 0xffffffbf;
  166. AC3PPDU_RL_time[k + CH1_out].LT_state |= 0x00000001;
  167. orderFlag[k]=true;
  168. }
  169. }
  170. }
  171. }
  172. #else
  173. #if SUPPORT_DETECTION
  174. if(detection_value == false) // duan lu qi shi fou zai xian
  175. {
  176. for(int i = 0; i < Output_ChN_default;i++)
  177. {
  178. AC3PPDU_RL_time[i + CH1_out].LT_state &=0xffffff7e;
  179. orderFlag[i]=true;
  180. }
  181. }
  182. #endif
  183. #endif
  184. #if (SUPPORT_ZERO_LINE && SUPPORT_RELAY_CTRL)
  185. if(orderFlag_N)
  186. {
  187. RL_N_now_state = AC3PPDU_RL_N_time.LT_state & 0x00000001 ;
  188. RL_N_last_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr] & 0x00000001;
  189. if(RL_N_now_state != RL_N_last_state)
  190. {
  191. if(RL_N_now_state > 0)
  192. {
  193. RL_N_ON_flag = 1;
  194. RL_N_OFF_flag = 0;
  195. if((AC3PPDU_RL_N_time.LT_state & 0x40) > 0)
  196. {
  197. RL_N_delay_Limit = AC3PPDU_RL_N_time.RL_ontime *1000;
  198. RL_N_begin_delay_flag = 1;
  199. RL_N_end_delay_flag = 0;
  200. }else
  201. {
  202. RL_N_delay_Limit = 0;
  203. RL_N_begin_delay_flag = 0;
  204. RL_N_end_delay_flag = 1;
  205. }
  206. }else
  207. {
  208. RL_N_ON_flag = 0;
  209. RL_N_OFF_flag = 1;
  210. if((AC3PPDU_RL_N_time.LT_state & 0x80) > 0)
  211. {
  212. RL_N_delay_Limit = AC3PPDU_RL_N_time.RL_offtime *1000;
  213. RL_N_begin_delay_flag = 1;
  214. RL_N_end_delay_flag = 0;
  215. }else
  216. {
  217. RL_N_delay_Limit = 0;
  218. RL_N_begin_delay_flag = 0;
  219. RL_N_end_delay_flag = 1;
  220. }
  221. }
  222. }else
  223. {
  224. RL_N_delay_Limit = 0;
  225. RL_N_begin_delay_flag = 0;
  226. RL_N_end_delay_flag = 0;
  227. RL_N_ON_flag = 0;
  228. RL_N_OFF_flag = 0;
  229. }
  230. orderFlag_N = false;
  231. AC3PPDU_RL_N_time.LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr];
  232. }
  233. #endif
  234. for(int k = 0;k < Output_ChN_default;k++)
  235. {
  236. if(orderFlag[k])
  237. {
  238. RL_now_state[k] = AC3PPDU_RL_time[k + CH1_out].LT_state & 0x00000001;
  239. RL_last_state[k] = AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + k] & 0x00000001;
  240. if(RL_now_state[k] != RL_last_state[k])
  241. {
  242. if(RL_now_state[k] > 0)
  243. {
  244. RL_ON_flag[k] = 1;
  245. RL_OFF_flag[k] = 0;
  246. if((AC3PPDU_RL_time[k + CH1_out].LT_state & 0x40) > 0)//有延时
  247. {
  248. RL_delay_Limit[k] = AC3PPDU_RL_time[k + CH1_out].RL_ontime * 1000;//秒转成毫秒
  249. RL_begin_delay_flag[k] = 1;
  250. RL_end_delay_flag[k] = 0;
  251. }else//无延时
  252. {
  253. RL_begin_delay_flag[k] = 0;
  254. RL_end_delay_flag[k] = 1;
  255. RL_delay_Limit[k] = 0;
  256. }
  257. }else
  258. {
  259. RL_OFF_flag[k] = 1;
  260. RL_ON_flag[k] = 0;
  261. if((AC3PPDU_RL_time[k + CH1_out].LT_state & 0x80) > 0)//有延时
  262. {
  263. RL_begin_delay_flag[k] = 1;
  264. RL_end_delay_flag[k] = 0;
  265. RL_delay_Limit[k] = AC3PPDU_RL_time[k + CH1_out].RL_offtime * 1000;//秒转成毫秒
  266. }else//无延时
  267. {
  268. RL_begin_delay_flag[k] = 0;
  269. RL_end_delay_flag[k] = 1;
  270. }
  271. }
  272. }
  273. else{
  274. RL_delay_Limit[k] = 0;
  275. RL_begin_delay_flag[k] = 0;
  276. RL_end_delay_flag[k] = 0;
  277. RL_ON_flag[k] = 0;
  278. RL_OFF_flag[k] = 0;
  279. }
  280. }
  281. orderFlag[k]=false;
  282. AC3PPDU_RL_time[k + CH1_out].LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + k];
  283. }
  284. #if SUPPORT_ZERO_LINE
  285. if(RL_N_end_delay_flag > 0)
  286. {
  287. RL_N_end_delay_flag = 0;
  288. RL_N_begin_delay_flag = 0;
  289. if(RL_N_ON_flag > 0)
  290. {
  291. RL_N_ON_flag = 0;
  292. DB_Out4_H;
  293. AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr] = (AC3PPDU_RL_N_time.FT_state | 0x00000001);
  294. }else if(RL_N_OFF_flag > 0)
  295. {
  296. RL_N_OFF_flag = 0;
  297. DB_Out4_L;
  298. AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr] = (AC3PPDU_RL_N_time.FT_state & 0xfffffffe);
  299. }else
  300. {
  301. ;
  302. }
  303. BUFF_Data;
  304. LOCK_Data;
  305. }
  306. #endif
  307. for(int i = 0;i < Output_ChN_default;i++)
  308. {
  309. if(RL_end_delay_flag[i] > 0)
  310. {
  311. RL_begin_delay_flag[i] = 0;
  312. RL_end_delay_flag[i] = 0;
  313. if(RL_ON_flag[i] > 0)
  314. {
  315. RL_ON_flag[i] = 0;
  316. switch (i)
  317. {
  318. case 0:
  319. DB_Out1_H;
  320. break;
  321. case 1:
  322. DB_Out2_H;
  323. break;
  324. case 2:
  325. DB_Out3_H;
  326. break;
  327. default:
  328. return;
  329. }
  330. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] = (AC3PPDU_RL_time[i + CH1_out].LT_state | 0x01);
  331. AC3PPDU_Modbus_Reg[Mb_Dbuff_OUTCH1_ST_Addr + (i % 3)] = AC3PPDU_RL_time[i + CH1_out].LT_state | 0x00000001;
  332. }else if(RL_OFF_flag[i] > 0)
  333. {
  334. RL_OFF_flag[i] = 0;
  335. switch (i)
  336. {
  337. case 0:
  338. DB_Out1_L;
  339. break;
  340. case 1:
  341. DB_Out2_L;
  342. break;
  343. case 2:
  344. DB_Out3_L;
  345. break;
  346. default:
  347. return;
  348. }
  349. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] = (AC3PPDU_RL_time[i + CH1_out].LT_state & 0xfffffffe);
  350. AC3PPDU_Modbus_Reg[Mb_Dbuff_OUTCH1_ST_Addr + (i % 3)] = AC3PPDU_RL_time[i + CH1_out].LT_state & 0xfffffffe;
  351. }else
  352. {
  353. ;
  354. }
  355. }
  356. BUFF_Data;
  357. //DelayNms(5);
  358. LOCK_Data;
  359. }
  360. RL_Allon_flag = false;
  361. RL_Alloff_flag = false;
  362. }
  363. #endif
  364. }
  365. static void LimiT_enable_check(uint8_t ch_x,uint32_t Lt_v)
  366. {
  367. uint16_t temp0 = 0;
  368. temp0 = Lt_v >> 1;
  369. if(ch_x > 3)
  370. {
  371. return;
  372. }
  373. //通道最大电压
  374. if((temp0 & AC3PPDU_Vmax_LT_enable) == AC3PPDU_Vmax_LT_enable)
  375. {
  376. AC3PPDU_Vmax_LTen_flag[ch_x] = 1;
  377. }
  378. else
  379. {
  380. AC3PPDU_Vmax_LTen_flag[ch_x] = 0;
  381. }
  382. //最小电压
  383. if((temp0 & AC3PPDU_Vmin_LT_enable) == AC3PPDU_Vmin_LT_enable)
  384. {
  385. AC3PPDU_Vmin_LTen_flag[ch_x] = 1;
  386. }
  387. else
  388. {
  389. AC3PPDU_Vmin_LTen_flag[ch_x] = 0;
  390. }
  391. //最大电流
  392. if((temp0 & AC3PPDU_Imax_LT_enable) == AC3PPDU_Imax_LT_enable)
  393. {
  394. AC3PPDU_Imax_LTen_flag[ch_x] = 1;
  395. }
  396. else
  397. {
  398. AC3PPDU_Imax_LTen_flag[ch_x] = 0;
  399. }
  400. //最大功率
  401. if((temp0 & AC3PPDU_Wmax_LT_enable) == AC3PPDU_Wmax_LT_enable)
  402. {
  403. AC3PPDU_Wmax_LTen_flag[ch_x] = 1;
  404. }
  405. else
  406. {
  407. AC3PPDU_Wmax_LTen_flag[ch_x] = 0;
  408. }
  409. //最大电量
  410. if((temp0 & AC3PPDU_kWhmax_LT_enable) == AC3PPDU_kWhmax_LT_enable)
  411. {
  412. AC3PPDU_kWhmax_LTen_flag[ch_x] = 1;
  413. }
  414. else
  415. {
  416. AC3PPDU_kWhmax_LTen_flag[ch_x] = 0;
  417. }
  418. }
  419. static void check_3_phse()
  420. {
  421. uint8_t Phase_3_Close_flag=0;
  422. if(3 == Phase_N){
  423. for(int i = 0 ; i < Output_ChN_default; i += 3 )
  424. {
  425. Phase_3_Close_flag = 0;
  426. for(int j = 1;j <= 3;j++)
  427. {
  428. if(RL_Func_statu[j+i] == 1)
  429. {
  430. Phase_3_Close_flag = 1;
  431. break;
  432. }
  433. }
  434. if(Phase_3_Close_flag)
  435. {
  436. for(int j = 1;j <= 3;j++)
  437. {
  438. RL_Func_statu[j+i] = 1;
  439. }
  440. }
  441. Phase_3_Close_flag = 0;
  442. }
  443. }
  444. }
  445. static void RL_Over_Func()
  446. {
  447. //check_3_phse();
  448. if(RL_All_Func)
  449. {
  450. for(int i = 0; i < Output_ChN_default;i++)
  451. {
  452. AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xffffff3e;
  453. orderFlag[i]=true;
  454. //orderFlag_N = true;
  455. }
  456. RL_All_Func = 0;
  457. return;
  458. }
  459. for(int i = 0; i < Output_ChN_default;i++)
  460. {
  461. if(RL_Func_statu[i+1])
  462. {
  463. AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_RL_time[i + CH1_out].LT_state &0xffffff3e;
  464. orderFlag[i]=true;
  465. RL_Func_statu[i+1] = 0;
  466. }
  467. }
  468. }
  469. static void key_io_control()
  470. {
  471. if(detection_value == true)
  472. {
  473. AC3PPDU_Modbus_Reg[Mb_Dbuff_Detection] = 0x1;
  474. }else
  475. {
  476. AC3PPDU_Modbus_Reg[Mb_Dbuff_Detection] = 0x0;
  477. }
  478. }
  479. int main(void)
  480. {
  481. app_init(&meta_data);
  482. InitSysTick();
  483. InitLED();
  484. InitKey();
  485. InitTimer();
  486. InitRelay();
  487. Init_74hc573();
  488. InitAT24Cxx();
  489. InitUART1(9600);
  490. InitCH448F();
  491. AC3PPDU_SlaveAddress = ReadKeyValue();
  492. eMBInit(MB_RTU, AC3PPDU_SlaveAddress, 0, 115200, MB_PAR_NONE);
  493. eMBEnable();
  494. key_io_init(NULL);
  495. AC3PPDU_active_chn = Output_ChN_default;
  496. for(int i = 1; i <= AC3PPDU_active_chn;i++)
  497. {
  498. hlw8110_init(i);
  499. }
  500. ReadEeprom();
  501. strcpy(infomation.date,__DATE__);
  502. strcat(infomation.date," ");
  503. strcat(infomation.date,__TIME__);
  504. strcpy(infomation.ver,VERSION);
  505. int size = sizeof(infomation);
  506. Devid_IDChalNum = AC3PPDU_Device_ID;
  507. Devid_IDChalNum = Devid_IDChalNum << 8;
  508. Devid_IDChalNum += Output_ChN_default;
  509. AC3PPDU_Modbus_Reg[Mb_Dbuff_DevAddr] = Devid_IDChalNum;
  510. infomation.channels = Output_ChN_default;
  511. flash_get_infomation(&infomation);
  512. AC3PPDU_RL_time[CH_in].LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_LT_ST_Addr];
  513. AC3PPDU_RL_time[CH_in].FT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr];
  514. LimiT_enable_check(CH_in,AC3PPDU_RL_time[CH_in].LT_state);
  515. Enable_74hc573_Output;
  516. // Fault_state_Last = Fault_state_Reg;
  517. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] = AC3PPDU_APlack_Fault + AC3PPDU_BPlack_Fault;
  518. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] += AC3PPDU_CPlack_Fault;
  519. for(int i = 0;i < Output_ChN_default;i++)
  520. {
  521. RL_last_state[i] = 0;
  522. AC3PPDU_RL_time[i + CH1_out].LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i];
  523. AC3PPDU_Modbus_Reg[Mb_Dbuff_CH1LT_ST_Addr + i] &= 0xfffffffe;
  524. AC3PPDU_RL_time[i + CH1_out].RL_ontime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Ton1_Addr + i];
  525. AC3PPDU_RL_time[i + CH1_out].RL_offtime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Toff1_Addr + i];
  526. LimiT_enable_check((i + CH1_out),AC3PPDU_RL_time[i + CH1_out].LT_state);
  527. orderFlag[i]=true;
  528. }
  529. #if SUPPORT_ZERO_LINE
  530. RL_N_last_state = 0;
  531. AC3PPDU_RL_N_time.LT_state = AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr]; // add by liyi
  532. AC3PPDU_Modbus_Reg[Mb_Dbuff_CHNLT_ST_Addr] &= 0xfffffffe;
  533. AC3PPDU_RL_N_time.RL_offtime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_ToffN_Addr]; // add by liyi
  534. AC3PPDU_RL_N_time.RL_ontime = AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_TonN_Addr]; // add by liyi
  535. #endif
  536. orderFlag_N = true;
  537. Fwdgt_Init();
  538. #if SUPPORT_DETECTION
  539. detection_value = get_detection();
  540. #endif
  541. uint32_t count = 0;
  542. while(1)
  543. {
  544. // CHK_JLINK();
  545. #if SUPPORT_RELAY_CTRL
  546. check_jlink();
  547. #endif
  548. eMBPoll();
  549. Fwdgt_reload();
  550. if(flash_flag == 1){
  551. LEDFlicker2();
  552. flash_flag = 0;
  553. #if SUPPORT_DETECTION
  554. detection_value = get_detection();
  555. #endif
  556. for(int j = 0 ; j < Hlw8110_CS;j++)
  557. read_Hlw8110(j,0);
  558. count ++;
  559. normal_running_time+=2;
  560. }
  561. if(count == 120) // 120 second recode
  562. {
  563. count = 0;
  564. for(int i = 0; i < Output_ChN_default ;i++)
  565. {
  566. int temp = i << 2;
  567. Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+0] = AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr+i] >> 24;
  568. Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+1] = AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr+i] >> 16;
  569. Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+2] = AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr+i] >> 8;
  570. Eeprom_Rbuf[ERom_TotalWh1_Addr+temp+3] = AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr+i];
  571. }
  572. AT24CxxWrite(ERom_TotalWh1_Addr,(Eeprom_Rbuf + ERom_TotalWh1_Addr),4*Output_ChN_default);
  573. }
  574. AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] = AC3PPDU_Output[CH1_out].AC_V;
  575. AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] = AC3PPDU_Output[CH2_out].AC_V;
  576. AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] = AC3PPDU_Output[CH3_out].AC_V;
  577. AC3PPDU_Modbus_Reg[Mb_Dbuff_IAP_Addr] = AC3PPDU_Output[CH1_out].AC_I;
  578. AC3PPDU_Modbus_Reg[Mb_Dbuff_IBP_Addr] = AC3PPDU_Output[CH2_out].AC_I;
  579. AC3PPDU_Modbus_Reg[Mb_Dbuff_ICP_Addr] = AC3PPDU_Output[CH3_out].AC_I;
  580. AC3PPDU_Modbus_Reg[Mb_Dbuff_WAP_Addr] = AC3PPDU_Output[CH1_out].AC_P;
  581. AC3PPDU_Modbus_Reg[Mb_Dbuff_WBP_Addr] = AC3PPDU_Output[CH2_out].AC_P;
  582. AC3PPDU_Modbus_Reg[Mb_Dbuff_WCP_Addr] = AC3PPDU_Output[CH3_out].AC_P;
  583. AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr] = hlw8110_base[CH1_out] + (hlw8110_store[CH1_out]*1000);
  584. AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhBP_Addr] = hlw8110_base[CH2_out] + (hlw8110_store[CH2_out]*1000);
  585. AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhCP_Addr] = hlw8110_base[CH3_out] + (hlw8110_store[CH3_out]*1000);
  586. for(int i = 0;i < (Output_ChN_default + 1);i++)
  587. {
  588. Fault_state_process(i);
  589. }
  590. #if SUPPORT_RELAY_CTRL
  591. RL_Over_Func();
  592. #endif
  593. MODbus_CMD_New();
  594. }
  595. }
  596. static void MODbus_CMD_New(void)
  597. {
  598. if(Modbus_Wr_buff[Wr_eeprom_cnt][0] > 0)
  599. {
  600. uint8_t i = 0;
  601. uint32_t temp_addr;
  602. uint32_t base_addr = Modbus_Wr_buff[Wr_eeprom_cnt][1];
  603. uint32_t data = Modbus_Wr_buff[Wr_eeprom_cnt][2];
  604. uint32_t value = 0;
  605. switch(base_addr)
  606. {
  607. case Mb_Dbuff_ViLit_max_Addr ... Mb_Dbuff_kWhiLit_max_Addr: //input votage max votage min current power coustermer add by liyi
  608. {
  609. temp_addr = base_addr - Mb_Dbuff_ViLit_max_Addr;
  610. temp_addr = temp_addr << 2;
  611. temp_addr += ERom_ViLit_max_Addr;
  612. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  613. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  614. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  615. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  616. AC3PPDU_Modbus_Reg[base_addr] = data;
  617. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  618. }
  619. break;
  620. case Mb_Dbuff_VLit1_max_Addr ... Mb_Dbuff_VLit9_max_Addr: //output voltage max threod for 1,2,3,4,5,6,7,8,9 channels
  621. {
  622. temp_addr = base_addr - Mb_Dbuff_VLit1_max_Addr;
  623. value = temp_addr;
  624. temp_addr = temp_addr << 2;
  625. temp_addr += ERom_VLit1_max_Addr;
  626. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  627. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  628. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  629. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  630. AC3PPDU_Modbus_Reg[base_addr] = data;
  631. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  632. {
  633. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Vmax_Threshould_Disable);
  634. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  635. }
  636. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  637. }
  638. break;
  639. case Mb_Dbuff_VLit1_min_Addr ... Mb_Dbuff_VLit9_min_Addr: //output voltage min thred for 1,2,3,4,5,6,7,8,9 channels
  640. {
  641. temp_addr = base_addr - Mb_Dbuff_VLit1_min_Addr;
  642. value = temp_addr;
  643. temp_addr = temp_addr << 2;
  644. temp_addr += ERom_VLit1_min_Addr;
  645. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  646. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  647. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  648. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  649. AC3PPDU_Modbus_Reg[base_addr] = data;
  650. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  651. {
  652. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Vmin_Threshould_Disable);
  653. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  654. }
  655. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  656. }
  657. break;
  658. case Mb_Dbuff_ILit1_max_Addr ... Mb_Dbuff_ILit9_max_Addr: // output current max throud for 1,2,3,4,5,6,7,8,9 channels
  659. {
  660. temp_addr = base_addr - Mb_Dbuff_ILit1_max_Addr;
  661. value = temp_addr;
  662. temp_addr = temp_addr << 2;
  663. temp_addr += ERom_ILit1_max_Addr;
  664. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  665. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  666. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  667. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  668. AC3PPDU_Modbus_Reg[base_addr] = data;
  669. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  670. {
  671. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Imax_Threshould_Disable);
  672. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  673. }
  674. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  675. }
  676. break;
  677. case Mb_Dbuff_WLit1_max_Addr ... Mb_Dbuff_WLit9_max_Addr: //output power max .....
  678. {
  679. temp_addr = base_addr - Mb_Dbuff_WLit1_max_Addr;
  680. value = temp_addr;
  681. temp_addr = temp_addr << 2;
  682. temp_addr += ERom_WLit1_max_Addr;
  683. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  684. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  685. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  686. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  687. AC3PPDU_Modbus_Reg[base_addr] = data;
  688. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  689. {
  690. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Wmax_Threshould_Disable);
  691. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  692. }
  693. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  694. }
  695. break;
  696. case Mb_Dbuff_kWhLit1_max_Addr ... Mb_Dbuff_kWhLit9_max_Addr: //output customers max .....
  697. {
  698. temp_addr = base_addr - Mb_Dbuff_kWhLit1_max_Addr;
  699. value = temp_addr;
  700. temp_addr = temp_addr << 2;
  701. temp_addr += ERom_kWhLit1_max_Addr;
  702. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  703. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  704. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  705. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  706. AC3PPDU_Modbus_Reg[base_addr] = data;
  707. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  708. {
  709. AC3PPDU_RL_time[value + CH1_out].LT_state &= (Shield_Kwhmax_Threshould_Disable);
  710. LimiT_enable_check((value + CH1_out),AC3PPDU_RL_time[value + CH1_out].LT_state);
  711. }
  712. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  713. }
  714. break;
  715. case Mb_Dbuff_RL_Allon_Addr: //relay all on
  716. {
  717. RL_Allon_flag = true;
  718. for(i = 0;i < Output_ChN_default;i++)
  719. {
  720. temp_addr = i << 1;
  721. Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x41;
  722. AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
  723. }
  724. AT24CxxWrite(ERom_CH1LT_ST_Addr,(Eeprom_Rbuf + ERom_CH1LT_ST_Addr),(2*Output_ChN_default));
  725. Eeprom_Rbuf[ERom_CHNLT_ST_Addr] = Eeprom_Rbuf[ERom_CHNLT_ST_Addr] | 0x41;
  726. AC3PPDU_RL_N_time.LT_state = Eeprom_Rbuf[ERom_CHNLT_ST_Addr];
  727. AT24CxxWrite(ERom_CHNLT_ST_Addr,(Eeprom_Rbuf + ERom_CHNLT_ST_Addr),2);
  728. }
  729. break;
  730. case Mb_Dbuff_RL_Alloff_Addr: //relay all off
  731. {
  732. RL_Alloff_flag = true;
  733. for(i = 0;i < Output_ChN_default;i++)
  734. {
  735. temp_addr = i << 1;
  736. Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] | 0x80;
  737. Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr] & 0xfe;
  738. AC3PPDU_RL_time[i + CH1_out].LT_state = Eeprom_Rbuf[ERom_CH1LT_ST_Addr + temp_addr];
  739. }
  740. AT24CxxWrite(ERom_CH1LT_ST_Addr,(Eeprom_Rbuf + ERom_CH1LT_ST_Addr),(2*Output_ChN_default));
  741. Eeprom_Rbuf[ERom_CHNLT_ST_Addr] = Eeprom_Rbuf[ERom_CHNLT_ST_Addr] | 0x80;
  742. Eeprom_Rbuf[ERom_CHNLT_ST_Addr] = Eeprom_Rbuf[ERom_CHNLT_ST_Addr] & 0xfe;
  743. AC3PPDU_RL_N_time.LT_state = Eeprom_Rbuf[ERom_CHNLT_ST_Addr];
  744. AT24CxxWrite(ERom_CHNLT_ST_Addr,(Eeprom_Rbuf + ERom_CHNLT_ST_Addr),2);
  745. }
  746. break;
  747. case Mb_Dbuff_LT_ST_Addr: //set input status
  748. {
  749. AC3PPDU_RL_time[CH_in].LT_state = data;
  750. Eeprom_Rbuf[ERom_LT_ST_Addr] = data;
  751. AC3PPDU_Modbus_Reg[base_addr] = data;
  752. AT24CxxWriteOneByte(ERom_LT_ST_Addr,Eeprom_Rbuf[ERom_LT_ST_Addr]);
  753. LimiT_enable_check(CH_in,AC3PPDU_RL_time[CH_in].LT_state);
  754. }
  755. break;
  756. case Mb_Dbuff_CH1LT_ST_Addr ... Mb_Dbuff_CHNLT_ST_Addr: //set output relay statues
  757. {
  758. temp_addr = base_addr - Mb_Dbuff_CH1LT_ST_Addr;
  759. if(temp_addr == 9) { //Ch N
  760. AC3PPDU_RL_N_time.LT_state = data;
  761. orderFlag_N = true;
  762. }else{
  763. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  764. {
  765. data &= (Shield_Vmax_Threshould_Disable);
  766. }
  767. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  768. {
  769. data &= (Shield_Vmin_Threshould_Disable);
  770. }
  771. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  772. {
  773. data &= (Shield_Imax_Threshould_Disable);
  774. }
  775. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  776. {
  777. data &= (Shield_Wmax_Threshould_Disable);
  778. }
  779. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  780. {
  781. data &= (Shield_Kwhmax_Threshould_Disable);
  782. }
  783. orderFlag[temp_addr]=true;
  784. AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
  785. LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
  786. }
  787. temp_addr = temp_addr << 1;
  788. temp_addr += ERom_CH1LT_ST_Addr;
  789. Eeprom_Rbuf[temp_addr] = data;
  790. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  791. }
  792. break;
  793. case Mb_Dbuff_OUTCH1_ST_Addr ... Mb_Dbuff_OUTCH3_ST_Addr: //set output channel relay's status
  794. {
  795. temp_addr = base_addr - Mb_Dbuff_OUTCH1_ST_Addr;
  796. //OutUnit_control_flag[temp_addr] = 1;
  797. temp_addr *= 3;
  798. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  799. {
  800. data &= (Shield_Vmax_Threshould_Disable);
  801. }
  802. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  803. {
  804. data &= (Shield_Vmin_Threshould_Disable);
  805. }
  806. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  807. {
  808. data &= (Shield_Imax_Threshould_Disable);
  809. }
  810. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  811. {
  812. data &= (Shield_Wmax_Threshould_Disable);
  813. }
  814. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + temp_addr] <= THRESHOULD_JUDGMENT)
  815. {
  816. data &= (Shield_Kwhmax_Threshould_Disable);
  817. }
  818. for(int i=0;i<Output_ChN_default;i++)
  819. {
  820. orderFlag[i]=true;
  821. }
  822. AC3PPDU_RL_time[temp_addr + CH1_out].LT_state = data;
  823. AC3PPDU_RL_time[temp_addr + CH2_out].LT_state = data;
  824. AC3PPDU_RL_time[temp_addr + CH3_out].LT_state = data;
  825. LimiT_enable_check((temp_addr + CH1_out),AC3PPDU_RL_time[temp_addr + CH1_out].LT_state);
  826. LimiT_enable_check((temp_addr + CH2_out),AC3PPDU_RL_time[temp_addr + CH2_out].LT_state);
  827. LimiT_enable_check((temp_addr + CH3_out),AC3PPDU_RL_time[temp_addr + CH3_out].LT_state);
  828. temp_addr = temp_addr << 1;
  829. Eeprom_Rbuf[temp_addr + ERom_CH1LT_ST_Addr] = data;
  830. Eeprom_Rbuf[temp_addr + ERom_CH2LT_ST_Addr] = data;
  831. Eeprom_Rbuf[temp_addr + ERom_CH3LT_ST_Addr] = data;
  832. AT24CxxWriteOneByte(temp_addr + ERom_CH1LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH1LT_ST_Addr]);
  833. AT24CxxWriteOneByte(temp_addr + ERom_CH2LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH2LT_ST_Addr]);
  834. AT24CxxWriteOneByte(temp_addr + ERom_CH3LT_ST_Addr,Eeprom_Rbuf[temp_addr + ERom_CH3LT_ST_Addr]);
  835. }
  836. break;
  837. case Mb_Dbuff_RL_Ton1_Addr ... Mb_Dbuff_RL_TonN_Addr: //set on status delay for 1,2,3,4,5,6,7,8,9,N channels
  838. {
  839. temp_addr = base_addr - Mb_Dbuff_RL_Ton1_Addr;
  840. if(temp_addr == 9){ //Ch N add by liyi
  841. AC3PPDU_RL_N_time.RL_ontime = data;
  842. }else
  843. {
  844. AC3PPDU_RL_time[temp_addr + CH1_out].RL_ontime = data;
  845. }
  846. AC3PPDU_RL_N_time.RL_ontime = data;
  847. temp_addr += ERom_RL_Ton1_Addr;
  848. Eeprom_Rbuf[temp_addr] = data;
  849. Eeprom_Rbuf[ERom_RL_TonN_Addr] = data;
  850. AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
  851. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_TonN_Addr] = Eeprom_Rbuf[ERom_RL_TonN_Addr];
  852. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  853. AT24CxxWriteOneByte(ERom_RL_TonN_Addr,Eeprom_Rbuf[ERom_RL_TonN_Addr]);
  854. }
  855. break;
  856. case Mb_Dbuff_RL_Toff1_Addr ... Mb_Dbuff_RL_ToffN_Addr: //set off status delay for 1,2,3,4,5,6,7,8,9,N channels
  857. {
  858. temp_addr = base_addr - Mb_Dbuff_RL_Toff1_Addr;
  859. if(temp_addr == 9){
  860. AC3PPDU_RL_N_time.RL_offtime = data;
  861. }else {
  862. AC3PPDU_RL_time[temp_addr + CH1_out].RL_offtime = data;
  863. }
  864. AC3PPDU_RL_N_time.RL_offtime = data;
  865. temp_addr += ERom_RL_Toff1_Addr;
  866. Eeprom_Rbuf[temp_addr] = data;
  867. Eeprom_Rbuf[ERom_RL_ToffN_Addr] = data;
  868. AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
  869. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_ToffN_Addr] = Eeprom_Rbuf[ERom_RL_ToffN_Addr];
  870. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  871. AT24CxxWriteOneByte(ERom_RL_ToffN_Addr,Eeprom_Rbuf[ERom_RL_ToffN_Addr]);
  872. }
  873. break;
  874. case Mb_Dbuff_RL_Over_Ch1_Func ... Mb_Dbuff_RL_Over_Ch9_Func: //threod over limit operation
  875. {
  876. temp_addr = base_addr - Mb_Dbuff_RL_Over_Ch1_Func;
  877. temp_addr += ERom_RL_Over_Ch1_Addr;
  878. Eeprom_Rbuf[temp_addr] = data;
  879. AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
  880. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  881. }
  882. break;
  883. case Mb_Dbuff_Clear_Chn1_Consumer ... Mb_Dbuff_Clear_Chn9_Consumer:
  884. {
  885. if(data)
  886. {
  887. temp_addr = base_addr - Mb_Dbuff_Clear_Chn1_Consumer;
  888. hlw8110_base[temp_addr+CH1_out] = 0;
  889. hlw8110_store[temp_addr+CH1_out] = 0.0;
  890. }
  891. }
  892. case Mb_Dbuff_Clear_Chnall_Consumer:
  893. {
  894. if(data){
  895. for(i = 0; i < Output_ChN_default;i++)
  896. {
  897. hlw8110_base[i+CH1_out] = 0;
  898. hlw8110_store[i+CH1_out] = 0.0;
  899. }
  900. }
  901. }
  902. break;
  903. case Mb_Dbuff_All_ViLit_Max ... Mb_Dbuff_All_kWhiLit_Max:
  904. {
  905. temp_addr = base_addr - Mb_Dbuff_All_ViLit_Max;
  906. temp_addr = temp_addr << 2;
  907. temp_addr += ERom_VILit_All_max_Addr;
  908. Eeprom_Rbuf[temp_addr + 0] = data >> 24;
  909. Eeprom_Rbuf[temp_addr + 1] = data >> 16;
  910. Eeprom_Rbuf[temp_addr + 2] = data >> 8;
  911. Eeprom_Rbuf[temp_addr + 3] = data >> 0;
  912. AC3PPDU_Modbus_Reg[base_addr] = data;
  913. AT24CxxWrite(temp_addr,(Eeprom_Rbuf + temp_addr),4);
  914. switch (base_addr - Mb_Dbuff_All_ViLit_Max)
  915. {
  916. case 0:
  917. {
  918. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  919. {
  920. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Vmax_Threshould_Disable);
  921. }else
  922. {
  923. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_Vmax_Threshould_enable);
  924. }
  925. }
  926. break;
  927. case 1:
  928. {
  929. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  930. {
  931. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Vmin_Threshould_Disable);
  932. }else
  933. {
  934. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_Vmin_Threshould_enable);
  935. }
  936. }
  937. break;
  938. case 2:
  939. {
  940. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  941. {
  942. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Imax_Threshould_Disable);
  943. }else
  944. {
  945. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_Imax_Threshould_enable);
  946. }
  947. }
  948. break;
  949. case 3:
  950. {
  951. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  952. {
  953. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Wmax_Threshould_Disable);
  954. }else
  955. {
  956. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_Wmax_Threshould_enable);
  957. }
  958. }
  959. break;
  960. case 4:
  961. {
  962. if(AC3PPDU_Modbus_Reg[base_addr] <= THRESHOULD_JUDGMENT)
  963. {
  964. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] &= (Shield_Kwhmax_Threshould_Disable);
  965. }else
  966. {
  967. AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] |= (Shield_kWhmax_Threshould_enable);
  968. }
  969. }
  970. break;
  971. }
  972. }
  973. break;
  974. case Mb_Dbuff_All_OverFunc:
  975. {
  976. temp_addr = base_addr - Mb_Dbuff_All_OverFunc;
  977. temp_addr += Mb_Dbuff_All_OverFunc;
  978. Eeprom_Rbuf[temp_addr] = data;
  979. AC3PPDU_Modbus_Reg[base_addr] = Eeprom_Rbuf[temp_addr];
  980. AT24CxxWriteOneByte(temp_addr,Eeprom_Rbuf[temp_addr]);
  981. }
  982. break;
  983. case Mb_Dbuff_break_Addr:
  984. {
  985. break_2_boot_upgreade();
  986. }
  987. break;
  988. default:
  989. break;
  990. }
  991. Modbus_Wr_buff[Wr_eeprom_cnt][0] = 0;
  992. //Wr_eeprom_begin_flag = true;
  993. }
  994. Wr_eeprom_cnt++;
  995. if(Wr_eeprom_cnt >= Mb_Wcmd_Width)
  996. {
  997. Wr_eeprom_cnt = 0;
  998. }
  999. }
  1000. //static void MODbus_CMD_New(void)
  1001. //{
  1002. // if(Modbus_Wr_buff[Wr_eeprom_cnt][0] > 0)
  1003. // {
  1004. // uint8_t i = 0;
  1005. // uint32_t temp_addr;
  1006. // uint32_t base_addr = Modbus_Wr_buff[Wr_eeprom_cnt][1];
  1007. // uint32_t data = Modbus_Wr_buff[Wr_eeprom_cnt][2];
  1008. // uint32_t value = 0;
  1009. //
  1010. // switch(base_addr)
  1011. // {
  1012. // case Mb_Dbuff_RL_Allon_Addr:
  1013. // {
  1014. // DB_Out1_H;
  1015. // DB_Out2_H;
  1016. // DB_Out3_H;
  1017. // BUFF_Data;
  1018. // LOCK_Data;
  1019. // }
  1020. // break;
  1021. // case Mb_Dbuff_RL_Alloff_Addr:
  1022. // {
  1023. // DB_Out1_L;
  1024. // DB_Out2_L;
  1025. // DB_Out3_L;
  1026. // BUFF_Data;
  1027. // LOCK_Data;
  1028. // }
  1029. // break;
  1030. // }
  1031. // Modbus_Wr_buff[Wr_eeprom_cnt][0] = 0;
  1032. // }
  1033. // Wr_eeprom_cnt++;
  1034. // if(Wr_eeprom_cnt >= Mb_Wcmd_Width)
  1035. // {
  1036. // Wr_eeprom_cnt = 0;
  1037. // }
  1038. //}
  1039. static void Fault_state_process(uint8_t ch_x)
  1040. {
  1041. uint16_t i = 0;
  1042. if(ch_x != CH_in)
  1043. i = (ch_x -1)<< 3;
  1044. if(ch_x == CH_in)
  1045. {
  1046. uint32_t sort_buff[3] = {0};
  1047. uint32_t Vmax = 0;
  1048. uint32_t Vmin = 0;
  1049. sort_buff[0] = AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr];
  1050. sort_buff[1] = AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr];
  1051. sort_buff[2] = AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr];
  1052. Vmax = (sort_buff[0] >= sort_buff[1]) ? sort_buff[0] :sort_buff[1];
  1053. Vmax = (Vmax >= sort_buff[2]) ? Vmax : sort_buff[2];
  1054. Vmin = (sort_buff[0] <= sort_buff[1]) ? sort_buff[0] :sort_buff[1];
  1055. Vmin = (Vmin <= sort_buff[2]) ? Vmin : sort_buff[2];
  1056. if((Vmin < AC3PPDU_Lack_Voltage) && (Vmax != 0) && (Vmax > (AC3PPDU_Lack_Voltage*2)))
  1057. {
  1058. uint32_t v_mid = AC3PPDU_Lack_Voltage *2;
  1059. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] < v_mid)
  1060. {
  1061. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackA_Addr] = 1;
  1062. }
  1063. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] < v_mid)
  1064. {
  1065. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackB_Addr] = 1;
  1066. }
  1067. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] < v_mid)
  1068. {
  1069. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackC_Addr] =1;
  1070. }
  1071. }else
  1072. {
  1073. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackA_Addr] = 0;
  1074. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackB_Addr] = 0;
  1075. AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_LackC_Addr] = 0;
  1076. }
  1077. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_Vmax_Threshould_enable) > 0)
  1078. {
  1079. if(AC_BASE[0] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_ViLit_Max])
  1080. {
  1081. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Vmax_Fault;
  1082. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmin_NFault;
  1083. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_V_Max_Func_enable)
  1084. {
  1085. RL_All_Func = 1;
  1086. }
  1087. }else if(AC_BASE[0] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_ViLit_Min])
  1088. {
  1089. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmax_NFault;
  1090. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmin_NFault;
  1091. }else
  1092. {
  1093. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmax_NFault;
  1094. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Vmin_Fault;
  1095. }
  1096. }
  1097. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_Vmin_Threshould_enable) > 0)
  1098. {
  1099. if(AC_BASE[0] < AC3PPDU_Modbus_Reg[Mb_Dbuff_All_ViLit_Min])
  1100. {
  1101. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Vmin_Fault;
  1102. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_V_Min_Func_enable)
  1103. {
  1104. RL_All_Func = 1;
  1105. }
  1106. }
  1107. else//小于最小
  1108. {
  1109. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Vmin_NFault;
  1110. }
  1111. }
  1112. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_Imax_Threshould_enable) > 0)
  1113. {
  1114. if(AC_BASE[1] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_IiLit_Max])
  1115. {
  1116. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Imax_Fault;
  1117. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_I_Max_Func_enable)
  1118. {
  1119. RL_All_Func = 1;
  1120. }
  1121. }
  1122. else
  1123. {
  1124. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Imax_NFault;
  1125. }
  1126. }
  1127. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_Wmax_Threshould_enable) > 0)
  1128. {
  1129. if(AC_BASE[2] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_WiLit_Max])
  1130. {
  1131. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_Wmax_Fault;
  1132. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_P_Max_Func_enable)
  1133. {
  1134. RL_All_Func = 1;
  1135. }
  1136. }
  1137. else
  1138. {
  1139. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_Wmax_NFault;
  1140. }
  1141. }
  1142. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ALL_LT_ST_Addr] & Shield_kWhmax_Threshould_enable) > 0)
  1143. {
  1144. if(AC_BASE[3] > AC3PPDU_Modbus_Reg[Mb_Dbuff_All_kWhiLit_Max])
  1145. {
  1146. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] |= AC3PPDU_kWhmax_Fault;
  1147. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_All_OverFunc] & AC3PPDU_Over_C_Max_Func_enable)
  1148. {
  1149. RL_All_Func = 1;
  1150. }
  1151. }
  1152. else
  1153. {
  1154. AC3PPDU_Modbus_Reg[Mb_Dbuff_Tr_All_FT_ST_Addr] &= AC3PPDU_kWhmax_NFault;
  1155. }
  1156. }
  1157. return;
  1158. }
  1159. ////电压最大、最小、缺相阈值使能,进行判断
  1160. if(AC3PPDU_Vmax_LTen_flag[ch_x] > 0)
  1161. {
  1162. if(ch_x > CH_in)//输出通道
  1163. {
  1164. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_max_Addr + ch_x-1])//大于最大
  1165. {
  1166. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Vmax_Fault;
  1167. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmin_NFault;
  1168. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func+ch_x-1] & (AC3PPDU_Over_V_Max_Func_enable)) //is or not open func
  1169. {
  1170. RL_Func_statu[ch_x] = 1;
  1171. }
  1172. }
  1173. else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + ch_x-1])//大于最小,小于最大,正常
  1174. {
  1175. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmax_NFault;
  1176. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmin_NFault;
  1177. }
  1178. else//小于最小
  1179. {
  1180. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmax_NFault;
  1181. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Vmin_Fault;
  1182. }
  1183. }
  1184. else//输入通道
  1185. {
  1186. //A相
  1187. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_max_Addr])//超限
  1188. {
  1189. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AVmax_Fault;
  1190. }
  1191. else
  1192. {
  1193. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmax_NFault;
  1194. }
  1195. //B相
  1196. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_max_Addr])//超限
  1197. {
  1198. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BVmax_Fault;
  1199. }
  1200. else
  1201. {
  1202. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmax_NFault;
  1203. }
  1204. //C相
  1205. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_max_Addr])//超限
  1206. {
  1207. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CVmax_Fault;
  1208. }
  1209. else
  1210. {
  1211. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmax_NFault;
  1212. }
  1213. }
  1214. }
  1215. else
  1216. {
  1217. if(ch_x > CH_in)
  1218. {
  1219. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmax_NFault;
  1220. }
  1221. else
  1222. {
  1223. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmax_NFault;
  1224. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmax_NFault;
  1225. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmax_NFault;
  1226. }
  1227. }
  1228. //最小电压
  1229. if(AC3PPDU_Vmin_LTen_flag[ch_x] > 0)
  1230. {
  1231. if(ch_x > CH_in)//输出通道
  1232. {
  1233. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + i] < AC3PPDU_Modbus_Reg[Mb_Dbuff_VLit1_min_Addr + ch_x -1])//大于最大 revice by liyi max -> min
  1234. {
  1235. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Vmin_Fault;
  1236. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func + ch_x - 1] & (AC3PPDU_Over_V_Min_Func_enable)) //is or not open func add by liyi
  1237. {
  1238. RL_Func_statu[ch_x] = 1;
  1239. }
  1240. }
  1241. else//小于最小
  1242. {
  1243. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmin_NFault;
  1244. }
  1245. }
  1246. else//输入通道
  1247. {
  1248. //A相
  1249. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_min_Addr])//
  1250. {
  1251. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmin_NFault;
  1252. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_APlack_NFault;
  1253. }
  1254. else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] > 1000)
  1255. {
  1256. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AVmin_Fault;
  1257. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_APlack_NFault;
  1258. }
  1259. else
  1260. {
  1261. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmin_NFault;
  1262. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_APlack_Fault;
  1263. }
  1264. //B相
  1265. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_min_Addr])//
  1266. {
  1267. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmin_NFault;
  1268. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BPlack_NFault;
  1269. }
  1270. else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] > 1000)
  1271. {
  1272. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BVmin_Fault;
  1273. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BPlack_NFault;
  1274. }
  1275. else
  1276. {
  1277. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmin_NFault;
  1278. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BPlack_Fault;
  1279. }
  1280. //C相
  1281. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ViLit_min_Addr])//超限
  1282. {
  1283. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmin_NFault;
  1284. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CPlack_NFault;
  1285. }
  1286. else if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] > 1000)
  1287. {
  1288. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CVmin_Fault;
  1289. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CPlack_NFault;
  1290. }
  1291. else
  1292. {
  1293. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmin_NFault;
  1294. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CPlack_Fault;
  1295. }
  1296. }
  1297. }
  1298. else
  1299. {
  1300. if(ch_x > CH_in)
  1301. {
  1302. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Vmin_NFault;
  1303. }
  1304. else
  1305. {
  1306. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AVmin_NFault;
  1307. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BVmin_NFault;
  1308. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CVmin_NFault;
  1309. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VAP_Addr] > 1000)
  1310. {
  1311. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_APlack_NFault;
  1312. }
  1313. else
  1314. {
  1315. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_APlack_Fault;
  1316. }
  1317. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VBP_Addr] > 1000)
  1318. {
  1319. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BPlack_NFault;
  1320. }
  1321. else
  1322. {
  1323. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BPlack_Fault;
  1324. }
  1325. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_VCP_Addr] > 1000)
  1326. {
  1327. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CPlack_NFault;
  1328. }
  1329. else
  1330. {
  1331. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CPlack_Fault;
  1332. }
  1333. }
  1334. }
  1335. //电流最大
  1336. if(AC3PPDU_Imax_LTen_flag[ch_x] > 0)
  1337. {
  1338. if(ch_x > CH_in)//输出通道
  1339. {
  1340. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + 1 + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_ILit1_max_Addr + ch_x -1])
  1341. {
  1342. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Imax_Fault;
  1343. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func + ch_x-1] & (AC3PPDU_Over_I_Max_Func_enable)) //is or not open func add by liyi
  1344. {
  1345. RL_Func_statu[ch_x] = 1;
  1346. }
  1347. }
  1348. else
  1349. {
  1350. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Imax_NFault;
  1351. }
  1352. }
  1353. else//输入通道
  1354. {
  1355. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_IAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_IiLit_max_Addr]))//超限
  1356. {
  1357. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AImax_Fault;
  1358. }
  1359. else
  1360. {
  1361. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AImax_NFault;
  1362. }
  1363. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_IBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_IiLit_max_Addr]))//超限
  1364. {
  1365. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BImax_Fault;
  1366. }
  1367. else
  1368. {
  1369. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BImax_NFault;
  1370. }
  1371. if((AC3PPDU_Modbus_Reg[Mb_Dbuff_ICP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_IiLit_max_Addr]))//超限
  1372. {
  1373. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CImax_Fault;
  1374. }
  1375. else
  1376. {
  1377. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CImax_NFault;
  1378. }
  1379. }
  1380. }
  1381. else
  1382. {
  1383. if(ch_x > CH_in)
  1384. {
  1385. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Imax_NFault;
  1386. }
  1387. else
  1388. {
  1389. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AImax_NFault;
  1390. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BImax_NFault;
  1391. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CImax_NFault;
  1392. }
  1393. }
  1394. //功率最大
  1395. if(AC3PPDU_Wmax_LTen_flag[ch_x] > 0)
  1396. {
  1397. if(ch_x > CH_in)//输出通道
  1398. {
  1399. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + 2 + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WLit1_max_Addr + ch_x -1])
  1400. {
  1401. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_Wmax_Fault;
  1402. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func + ch_x-1] & (AC3PPDU_Over_P_Max_Func_enable)) //is or not open func add by liyi
  1403. {
  1404. RL_Func_statu[ch_x] = 1;
  1405. }
  1406. }
  1407. else
  1408. {
  1409. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Wmax_NFault;
  1410. }
  1411. }
  1412. else//输入通道
  1413. {
  1414. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1415. {
  1416. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AWmax_Fault;
  1417. }
  1418. else
  1419. {
  1420. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AWmax_NFault;
  1421. }
  1422. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1423. {
  1424. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BWmax_Fault;
  1425. }
  1426. else
  1427. {
  1428. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BWmax_NFault;
  1429. }
  1430. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_WCP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1431. {
  1432. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CWmax_Fault;
  1433. }
  1434. else
  1435. {
  1436. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CWmax_NFault;
  1437. }
  1438. }
  1439. }
  1440. else
  1441. {
  1442. if(ch_x > CH_in)
  1443. {
  1444. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_Wmax_NFault;
  1445. }
  1446. else
  1447. {
  1448. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AWmax_NFault;
  1449. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BWmax_NFault;
  1450. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CWmax_NFault;
  1451. }
  1452. }
  1453. //电量最大
  1454. if(AC3PPDU_kWhmax_LTen_flag[ch_x] > 0)
  1455. {
  1456. if(ch_x > CH_in)//输出通道
  1457. {
  1458. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_Out1Para_Addr + 6 + i] > AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhLit1_max_Addr + ch_x-1])
  1459. {
  1460. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] |= AC3PPDU_kWhmax_Fault;
  1461. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_RL_Over_Ch1_Func + ch_x-1] & (AC3PPDU_Over_C_Max_Func_enable)) //is or not open func add by liyi
  1462. {
  1463. RL_Func_statu[ch_x] = 1;
  1464. }
  1465. }
  1466. else
  1467. {
  1468. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_kWhmax_NFault;
  1469. }
  1470. }
  1471. else//输入通道
  1472. {
  1473. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhAP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1474. {
  1475. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_AkWhmax_Fault;
  1476. }
  1477. else
  1478. {
  1479. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AkWhmax_NFault;
  1480. }
  1481. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhBP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1482. {
  1483. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_BkWhmax_Fault;
  1484. }
  1485. else
  1486. {
  1487. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BkWhmax_NFault;
  1488. }
  1489. if(AC3PPDU_Modbus_Reg[Mb_Dbuff_kWhCP_Addr] > AC3PPDU_Modbus_Reg[Mb_Dbuff_WiLit_max_Addr])//超限
  1490. {
  1491. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] |= AC3PPDU_CkWhmax_Fault;
  1492. }
  1493. else
  1494. {
  1495. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CkWhmax_NFault;
  1496. }
  1497. }
  1498. }
  1499. else
  1500. {
  1501. if(ch_x > CH_in)
  1502. {
  1503. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr + ch_x] &= AC3PPDU_kWhmax_NFault;
  1504. }
  1505. else
  1506. {
  1507. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_AkWhmax_NFault;
  1508. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_BkWhmax_NFault;
  1509. AC3PPDU_Modbus_Reg[Mb_Dbuff_FT_ST_Addr] &= AC3PPDU_CkWhmax_NFault;
  1510. }
  1511. }
  1512. }
  1513. #ifdef USE_FULL_ASSERT
  1514. void assert_failed(uint8_t* file, uint32_t line)
  1515. {
  1516. while (1);
  1517. }
  1518. #else
  1519. void __aeabi_assert(const char * x1, const char * x2, int x3)
  1520. {
  1521. (void)x3;
  1522. }
  1523. #endif